NDLI: Design of a 3.5-GHz OOK CMOS transmitter with triangular pulse shaping

Content Provider	IEEE Xplore Digital Library
Author	Hyun Kim Jongsik Kim Jinsup Kim Hajoong Chung Hyunchol Shin
Copyright Year	2009
Description	Author affiliation: Korea Electronics Technology Institute, Seongnam 463-816, Korea (Jinsup Kim; Hajoong Chung) \|\| High-Speed Integrated Circuits and Systems Lab., Kwangwoon University, Seoul 139-701, Korea (Hyun Kim; Jongsik Kim; Hyunchol Shin)
Abstract	A low-power CMOS on-off keying (OOK) transmitter employing a triangular pulse shaping scheme is presented. The proposed pulse shaping circuit is based on a current-reused common-source stage, whose gain is controlled by modulating the gate-source voltage in a triangular form. The triangular control signal is generated by an opamp-based integrator. The proposed pulse shaping scheme can effectively support variable data rate. A 3.5-GHz OOK transmitter circuit adopting the proposed pulse shaping scheme is designed in a 0.13 μm CMOS process. It successfully modulates digital data from 100 kbps to 10 Mbps and delivers an output power of +2.5 dBm. The total current consumption is 4.17 mA from a 1.2 V supply voltage, of which only 0.57 mA is dissipated at the transmitter core excluding the output buffer.
Starting Page	104
Ending Page	107
File Size	611326
Page Count	4
File Format	PDF
ISBN	9781424450343
DOI	10.1109/SOCDC.2009.5423886
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-11-22
Publisher Place	Korea (South)
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Digital modulation Circuits pulse shaping CMOS process OOK Voltage control Pulse modulation CMOS Shape control Transmitters Signal generators Pulse shaping methods Power generation transmitter
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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