NDLI: An analytic decision method for the feed-forward equalizer tap-coefficients at transmitter

Content Provider	IEEE Xplore Digital Library
Author	Soo-Min Lee Jae-Yoon Sim Hong-June Park
Copyright Year	2009
Description	Author affiliation: Dep. EE., Pohang University of Science and Technology, Pohang, Korea (Soo-Min Lee; Jae-Yoon Sim; Hong-June Park)
Abstract	An approach to determine the tap-coefficients of a feed-forward equalizer (FFE) without the error accumulation is proposed. The simple-minded method of taking the negative values of the pulse response as the FFE tap-coefficients generates the error terms accumulated from the previous time points which are two data-periods ahead or further in the past, irrespective of the number of tap-coefficients. This error accumulation is induced because the added components for FFE compensation also experience the intersymbol interference (ISI). For the channel with the pre-cursor components, the situation becomes worse and the error terms are accumulated from all the previous time points which are one data-period ahead and further in the past. In this work, an analytic method is proposed to decide the FFE tap-coefficients, which guarantees no error terms accumulated from the time points up to the data-period times the number of tap-coefficients. In this way, the accumulated error terms are significantly reduced compared to the simple-minded method. The proposed method was applied to a FR4 PCB transmission line with the length ranging from 40cm to 100cm, and with the non-zero pre-cursor components at the data rate of 5Gbps. The proposed method achieved the voltage eye-opening of 46% and 50% for the 2-tap and 4-tap FFE, respectively, with the channel length of 100cm, while the simple-minded method gives a zero voltage eye-opening.
Starting Page	400
Ending Page	403
File Size	2062807
Page Count	4
File Format	PDF
ISBN	9781424450343
DOI	10.1109/SOCDC.2009.5423871
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-11-22
Publisher Place	Korea (South)
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	equalization high-speed Decision feedback equalizers Dispersion Pulse generation Transmission lines feed-forward equalizer (FFE) serial links Transmitters Intersymbol interference Dielectric losses Voltage Propagation losses tap-coefficients Feedforward systems transmitter
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A 10Gb/s Equalizer with Decision Feedback for High Speed Serial Links

A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology

A 19-Gb/s Serial Link Receiver With Both 4-Tap FFE and 5-Tap DFE Functions in 45-nm SOI CMOS

Equalizer implementation for 10 Gbps serial data link in 90 nm CMOS technology

Two enhanced decision feedback equalizers for 10Gb/s optical communications

An improved equalization circuit for 10-Gb/s high-speed serial transmission over backplane channel

High-speed serial differential signaling links with commercial equalizer

A 1.62/2.7-Gb/s Adaptive Transmitter With Two-Tap Preemphasis Using a Propagation-Time Detector

A programmable pre-cursor ISI equalization circuit for high-speed serial link over highly lossy backplane channel

An analytic decision method for the feed-forward equalizer tap-coefficients at transmitter

Similar Documents

A 10Gb/s Equalizer with Decision Feedback for High Speed Serial Links

A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology

A 19-Gb/s Serial Link Receiver With Both 4-Tap FFE and 5-Tap DFE Functions in 45-nm SOI CMOS

Equalizer implementation for 10 Gbps serial data link in 90 nm CMOS technology

Two enhanced decision feedback equalizers for 10Gb/s optical communications

An improved equalization circuit for 10-Gb/s high-speed serial transmission over backplane channel

High-speed serial differential signaling links with commercial equalizer

A 1.62/2.7-Gb/s Adaptive Transmitter With Two-Tap Preemphasis Using a Propagation-Time Detector

A programmable pre-cursor ISI equalization circuit for high-speed serial link over highly lossy backplane channel

An analytic decision method for the feed-forward equalizer tap-coefficients at transmitter