NDLI: A novel de-embedding technique for On-Wafer characterization of RF CMOS

Content Provider	IEEE Xplore Digital Library
Author	Loo, X.S. Yeo, K.S. Chew, K.W.J. Chan, L.H.K. Ong, S.N. Do, M.A. Boon, C.C.
Copyright Year	2009
Description	Author affiliation: Nanyang Technological University, School of Electrical Electronic Engineering, Nanyang Avenue, Singapore 639798 (Loo, X.S.; Yeo, K.S.; Chew, K.W.J.; Chan, L.H.K.; Ong, S.N.; Do, M.A.; Boon, C.C.)
Abstract	A novel de-embedding technique based on general fixture model is proposed to accurately de-embed the test fixture parasitic for characterization of RF CMOS at high frequency. The method is able to avoid over-de-embedding errors that exist in conventional techniques by utilizing three Thru structures of zero length and one Open dummy test structures for accurate extraction of fixture parasitic. The de-embedding result is verified with Thru line replaced as intrinsic device and has been shown matching closer to the actual intrinsic Thru line than other compared techniques for frequency of up to 50 GHz.
Starting Page	29
Ending Page	32
File Size	369969
Page Count	4
File Format	PDF
ISBN	9781424450343
DOI	10.1109/SOCDC.2009.5423849
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-11-22
Publisher Place	Korea (South)
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Integrated circuit interconnections Circuit testing High frequency characterization RF CMOS Radio frequency Semiconductor device modeling Geometry Industrial electronics De-embedding Fixtures CMOS technology Silicon Fixture parasitic Scattering parameters
Content Type	Text
Resource Type	Article

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