NDLI: 0.7–1.8 GHz digital polar transmitter using a watt-class CMOS power amplifier and digital pulse width modulation with spurious signal reduction

Content Provider	IEEE Xplore Digital Library
Author	Nakatani, T. Kimball, D.F. Larson, L.E. Asbeck, P.M.
Copyright Year	2012
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Univ. California of San Diego, La Jolla, CA, USA (Nakatani, T.; Kimball, D.F.; Asbeck, P.M.) \|\| Sch. of Eng., Brown Univ., Providence, RI, USA (Larson, L.E.)
Abstract	A polar transmitter driven by digital input signals for envelope and phase is demonstrated, using a switched output resonator to achieve multiband operation. A new digital pulse width modulation algorithm is also shown to partially suppress spurious signals associated with the digital input envelope signal. The transmitter consists of a current-mode class-D power amplifier (CMCD PA), together with a buck converter with a dead-time generator for improved efficiency. The CMCD PA was tuned by switched capacitors that can handle up to 9V, and was measured to have 30-31 dBm output power with 31-35% drain efficiency under single-tone testing. The proposed spurious signal reduction technique works to partially suppress the quantization noise without increasing power consumption. Overall efficiencies of 27.1 / 25.6% were obtained at 30.2 / 28.9 dBm CW output powers and 850 / 1750 MHz carrier frequencies respectively. Spur suppression of 9-10 dB peak was achieved when the proposed algorithm was applied to WCDMA modulation.
Sponsorship	IEEE Electron Devices Soc.
Starting Page	349
Ending Page	352
File Size	387705
Page Count	4
File Format	PDF
ISBN	9781467323024
e-ISBN	9782874870286
e-ISBN	9782874870262
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-10-29
Publisher Place	Netherlands
Access Restriction	Subscribed
Rights Holder	European Microwave Assoc
Subject Keyword	CMOS Frequency modulation Transmitters dither digital pulse width modulation polar transmitters Power amplifiers Switches Power generation Clocks buck converters
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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