NDLI: A new three-level NPC inverter based on phase individual DC-link circuit and high quality digital SPWM control technology

Content Provider	IEEE Xplore Digital Library
Author	Liu Jian Yin Xianggen Zhang Zhe Xiong Qing
Copyright Year	2009
Description	Author affiliation: College of electric and electronics engineering of Huazhong Univ. of Sci. & Tech., Wuhan 430074 China (Liu Jian; Yin Xianggen; Zhang Zhe; Xiong Qing)
Abstract	Due to the existence of reverse recovery time of power diodes, the clamp diodes and di/dt-chokes diodes of three-level NPC inverter will enter the reverse recovery region at the same time, and the partial over-circuit phenomena will occur. This problem limits the output power of inverter system and do harm to the devices. To avoid this over-current problem, a new circuit implementation of 6kV three-level NPC inverter based on three phase individual DC-link is presented. Using this new circuit the partial over-current problem of traditional three-level NPC inverter can be solved. On the other hand, the security, stability and flexibility of three-level NPC inverter control system are much more complicated than traditional two-level system and low-voltage inverter. So the high reliability hardware and software based on layer organization structure has been put forward. This control scheme is realized with only a single FPGA chip and can provide an effective, flexible, and safe solution for high-power three-level NPC inverters. At last, some simulation and experimental results are presented to verify the advantages of the 6kV three-level NPC inverters.
Starting Page	732
Ending Page	736
File Size	1024371
Page Count	5
File Format	PDF
ISBN	9781424448869
DOI	10.1109/ICCCAS.2009.5250416
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-07-23
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Digital control Control systems Inverters Hardware Circuit stability Clamps Security Diodes Power generation Field programmable gate arrays
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

FPGA Implementation of a Multi-Level SPWM for Three-Level NPC Inverter

Field programmable gate array based three-phase PWM inverter

Hybrid Digital Control for Three Phase Rectifier- Inverter System

The study of FPGA-based three-level SVM NPC inverter

Study on Theory and Key Technologies of Full Digital SPWM Implementation for Three-Level Neutral Point Clamped Inverter

Simulation and generation of SPWM waveform using VHDL for FPGA interfaced H bridge power inverter

A new three-phase inverter power-factor correction (PFC) scheme using field programmable gate array

A development of 6kV three-level NPC inverters with novel DC-link circuit and optimal dead-time configuration

FRT capability of 100kHz single phase utility interactive inverter with FPGA based hardware controller

A new three-level NPC inverter based on phase individual DC-link circuit and high quality digital SPWM control technology

Similar Documents

FPGA Implementation of a Multi-Level SPWM for Three-Level NPC Inverter

Field programmable gate array based three-phase PWM inverter

Hybrid Digital Control for Three Phase Rectifier- Inverter System

The study of FPGA-based three-level SVM NPC inverter

Study on Theory and Key Technologies of Full Digital SPWM Implementation for Three-Level Neutral Point Clamped Inverter

Simulation and generation of SPWM waveform using VHDL for FPGA interfaced H bridge power inverter

A new three-phase inverter power-factor correction (PFC) scheme using field programmable gate array

A development of 6kV three-level NPC inverters with novel DC-link circuit and optimal dead-time configuration

FRT capability of 100kHz single phase utility interactive inverter with FPGA based hardware controller

A new three-level NPC inverter based on phase individual DC-link circuit and high quality digital SPWM control technology