NDLI: Representing topological structures for 3-D floorplanning

Content Provider	IEEE Xplore Digital Library
Author	Renshen Wang Young, E.F.Y. Chung-Kuan Cheng
Copyright Year	2009
Description	Author affiliation: University of California, San Diego, La Jolla, 92093-0404, USA (Renshen Wang; Chung-Kuan Cheng) \|\| The Chinese University of Hong Kong, Shatin, NT, China (Young, E.F.Y.)
Abstract	3-D VLSI circuit is becoming a hot topic because of its potential of enhancing performance, while it is also facing challenges such as the increased complexity on floorplanning and placement. Efficient 3-D floorplan representations are needed to handle the placement optimization in new circuit designs. We review and categorize some state-of-the-art 3-D representations, and propose a twin quaternary tree (TQT) model for 3-D mosaic floorplans, extending the twin binary tree [16]. Differences between 2-D and 3-D mosaic floorplans are discussed and some 3-D properties not existing in 2-D are revealed. Though the efficiency of the twin tree for optimization heuristics is still an open question, insights from the discussions and conclusions can be helpful for 3-D physical design.
Starting Page	1098
Ending Page	1102
File Size	4632927
Page Count	5
File Format	PDF
ISBN	9781424448869
DOI	10.1109/ICCCAS.2009.5250323
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-07-23
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit optimization Tree graphs Moore's Law Stacking Integrated circuit interconnections Binary trees Very large scale integration Encoding Circuit synthesis Design optimization
Content Type	Text
Resource Type	Article

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