NDLI: Clock Tree construction and buffer planning in Placement

Content Provider	IEEE Xplore Digital Library
Author	Renwei Liu Yici Cai Weixiang Shen
Copyright Year	2009
Description	Author affiliation: Department of Computer Science and Technology/Tsinghua University/Beijing, China (Renwei Liu; Yici Cai; Weixiang Shen)
Abstract	With decreasing of feature size of VLSI designs, clock buffers are becoming quite huge. However, buffers often can't be placed at ideal places because that traditionally clock network construction is performed after place-ment and at this time all cells are fixed. As a result, wire length and buffer numbers of clock net are increased. In this paper, a procedure called Buffered Clock Tree Aware Placement is proposed to consider clock network design in placement stage. Through register clustering and virtual clock tree construction, pseudo buffers are inserted in placement and deleted after that, so that white spaces are left for clock buffer insertion. Besides, registers in the same cluster are brought closer so that the performances of clock net, such as skew, delay and wire length, improves. The experiment results indicate an average of 22.40% improvement in skew, 7.26% improvement in delay and 2.10% improvement in wire length. Besides, the total distances of clock buffer moving during overlap removing shows an average of 17.24% improvement because of reserved white spaces.
Starting Page	1037
Ending Page	1041
File Size	1794752
Page Count	5
File Format	PDF
ISBN	9781424448869
DOI	10.1109/ICCCAS.2009.5250344
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-07-23
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Clocks
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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