NDLI: Hardware architecture for H.264/AVC INTRA 16×16 frame processing

Content Provider	IEEE Xplore Digital Library
Author	Loukil, H. Arous, S. Ben Atitallah, A. Kadionik, P. Masmoudi, N.
Copyright Year	2009
Description	Author affiliation: University of Sfax, National School of Engineering, BP W, 3038, TUNISIA (Loukil, H.; Arous, S.; Masmoudi, N.) \|\| University of Sfax, High Institute of Electronics and Communication, BP 868, 3018, TUNISIA (Ben Atitallah, A.) \|\| IMS laboratory - ENSEIRB - University Bordeaux 1 - CNRS UMR 5218, 351 Cours de la Libération, 33 405 Talence Cedex, FRANCE (Kadionik, P.)
Abstract	In this paper, we present an efficient H.264 / AVC Intra 16×16 Frame Coder System. The System achieves realtime performance for video conference applications. The INTRA 16×16 is composed by intra 16×16 prediction, integer transform, quantization AC, inverse integer transform, inverse quantization AC, quantization DC, hadamard, inverse quantization DC, and inverse integer transform. The proposed hardware is implemented in VHDL. The VHDL RTL code works at 160 MHz in an Altera Stratix II FPGA and it code 129 Mpixels per second. This work will be used as an Intellectual Property (IP) integrated in H.264/AVC encoder.
Starting Page	82
Ending Page	85
File Size	399663
Page Count	4
File Format	PDF
ISBN	9781424443208
DOI	10.1109/DTIS.2009.4938029
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-04-06
Publisher Place	Egypt
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	intra prediction Hardware Implementation Laboratories H.264 Quantization Videoconference integer transform VHDL Computer architecture Intellectual property Prediction algorithms Hardware Automatic voltage control Timing Field programmable gate arrays quantization
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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