NDLI: Inverse Integer Transform in H.264/AVC Intra-frame Encoder

Content Provider	IEEE Xplore Digital Library
Author	Nadeem, M. Wong, S. Kuzmanov, G.
Copyright Year	2011
Abstract	Real-time video compression applications such as Digital Video Camera (DVC), Television Studio Broadcast, and Surveillance video utilize the H.264/AVC video encoder in intra-only encoding mode. The H.264/AVC standard supports multiple intra-prediction modes to reduce spatial redundancy in the video frame. The intra-prediction process for a current pixels block requires the reconstructed pixels from the previously encoded blocks within the same video frame. Therefore, processing units with low latency and high-throughput are required in the processing chain of the intra-frame encoder to meet the real-time performance constraint. The inverse integer transform is on the critical path of the intra-frame encoder and is one of the compute-intensive processing unit in the intra-frame encoding loop. In this paper, for real-time video compression applications, we propose a low-latency, area-efficient and high-throughput inverse integer transform hardware architecture. The proposed design significantly reduces the latency penalty (2:67ns) of the inverse integer transform in the intra-frame processing chain. While working at clock frequency of 375 MHz, synthesized under 0:18um CMOS standard cell technology, it can easily meet the throughput requirement of real-time processing of HDTV resolutions and consumes only 7512 gates.
Starting Page	228
Ending Page	233
File Size	311862
Page Count	6
File Format	PDF
ISBN	9781424493579
DOI	10.1109/DELTA.2011.48
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-01-17
Publisher Place	New Zealand
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	low-latency Transforms area-efficient architecture Quantization Logic gates intra-frame encoder Automatic voltage control Hardware Encoding H.264/AVC inverse integer transform Pixel
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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