NDLI: Performance evaluation of MIC@R router for on-chip networks

Content Provider	IEEE Xplore Digital Library
Author	Ben-Tekaya, R. Baganne, A. Torki, K. Tourki, R.
Copyright Year	2009
Description	Author affiliation: LESTER Lab -CNRS, UBS University, BP 92116, 56321 Lorient, France (Baganne, A.) \|\| CMP, INPG, 46 Avenue Filex Viallet 38031, Grenoble Cedex, France (Torki, K.) \|\| Electronics and Micro-Electronics Lab, Faculty of Sciences at Monastir, 5000, Tunisia (Ben-Tekaya, R.; Tourki, R.)
Abstract	The paper presents a performance evaluation of MIC@R router for Networks-on-Chip (NoC) design. Its architecture offers lowest routing latency (1 cycle) and allows supporting several adaptive routing algorithms. The proposed router architecture is implemented in ASIC technology and evaluated in 2D Mesh networks with four routing schemes: Deterministic, Fully Adaptive (FA), Proximity Congestion Awareness (PCA) and Proximity Hot-Spot Awareness (PHSA). The last scheme is a novel routing technique that improves better the latency and throughput compared to others schemes. The obtained results show that our router, combined with different routing algorithms has efficient performances.
Starting Page	97
Ending Page	101
File Size	4878085
Page Count	5
File Format	PDF
ISBN	9781424443208
DOI	10.1109/DTIS.2009.4938033
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-04-06
Publisher Place	Egypt
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Application specific integrated circuits Virtual colonoscopy Buffer storage Network-on-a-chip Pipelines Communication system control Routing Throughput Delay Principal component analysis
Content Type	Text
Resource Type	Article

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