NDLI: Quantum transport based simulation and design optimization of a 10 nm FinFET

Content Provider	IEEE Xplore Digital Library
Author	Sabry, Y.M. Abdolkader, T.M. Farouk, W.F.
Copyright Year	2009
Description	Author affiliation: Department of Basic Sciences, Higher Institute of Technology, Benha University, Egypt (Abdolkader, T.M.) \|\| Mentor Graphics, Cairo, Egypt (Farouk, W.F.) \|\| Department of Electronics and Communication, Faculty of Engineering, Ain Shams, University, Egypt (Sabry, Y.M.)
Abstract	The International Technology Roadmap for Semiconductors (ITRS) projected value for the High Performance (HP) MOSFET channel length is 10 nm at the year 2016. The FinFET is expected to replace the conventional bulk MOSFET beyond the 22 nm node due to the latter's scaling challenges. In this article the design optimization of a 10 nm FinFET is considered. It is shown that the ITRS requirements for the FinFET's driving current and switching speed can be satisfied simultaneously. The on-current and switching speed can be as large as 6734 µA/µm and 24.4 THz compared to the 4590 µA/µm and 5.6 THz of the ITRS projections. It is also shown that the use of a mid-gap work function can satisfy the ITRS requirements. Moreover, factors for better manufacturability like relaxed extension lateral abruptness and increased fin thickness are also considered in the design.
Starting Page	125
Ending Page	129
File Size	344517
Page Count	5
File Format	PDF
ISBN	9781424443208
DOI	10.1109/DTIS.2009.4938039
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-04-06
Publisher Place	Egypt
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Insulation FinFET mid-gap work function DG MOSFET Design optimization Degradation Quantum computing NEGF Voltage MOSFET circuits FinFETs Leakage current extension lateral abruptness Manufacturing Logic devices
Content Type	Text
Resource Type	Article

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