NDLI: Supply voltage glitches effects on CMOS circuits

Content Provider	IEEE Xplore Digital Library
Author	Djellid-Ouar, A. Cathebras, G. Bancel, F.
Copyright Year	2006
Description	Author affiliation: LIRMM-UMR5506, Monlpellier (Djellid-Ouar, A.)
Abstract	Among the attacks applied on secure circuits, fault injection techniques consist in the use of a combination of environmental conditions that induce computational errors in the chip that can leak protected informations. The purpose of our study is to build an accurate model able to describe the behaviour of CMOS circuits in presence of deliberated short supply voltage variations. This behaviour depends strongly on the basic gates (combinational logic, registers...) that make up the circuit. In this paper, we show why D-flip-flop are resistant to power supply glitches occurring between clock transitions and we propose an approach to evaluate the basic elements sensitivities towards faults generated by power glitches. Our aimed model will consequently be dependent on this sensitivity
Starting Page	257
Ending Page	261
File Size	476255
Page Count	5
File Format	PDF
ISBN	0780397266
DOI	10.1109/DTIS.2006.1708651
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-09-05
Publisher Place	Tunisia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Semiconductor device modeling CMOS logic circuits Power supplies Voltage Logic gates Combinational circuits Registers Circuit faults Protection Clocks
Content Type	Text
Resource Type	Article

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