NDLI: Universal low/medium speed I/sup 2/C-slave transceiver: a detailed VLSI implementation

Content Provider	IEEE Xplore Digital Library
Author	Oudjida, A.K. Liacha, A. Benamrouche, D. Goudjil, M. Tiar, R. Ouchabane, A.
Copyright Year	2006
Description	Author affiliation: Centre de Developpement des Technol. Avancee, Algiers (Oudjida, A.K.)
Abstract	Based on a recent market study of an important number of I2 C devices, all fully compliant with the Philips $I^{2}C-bus$ specification, version 2.1, release January 2000, this paper introduces a detailed $I^{2}C-slave$ VLSI-architecture that incorporates all necessary features required by modern ASK/SoC applications, except high speed mode. The design is a general purpose solution offering viable ways to controlling $I^{2}C-bus$ and highly flexible to suit any particular needs. The purpose of this paper is to provide a full description of an up-to-date $I^{2}C-slave$ VLSI-implementation. All related issues, starting from the elaboration of initial specifications, till the final verifications and synthesis, are comprehensively discussed and justified. This includes all issues from basic architectural operations to final software drivers and application. The whole design code, either for synthesis or verification, is implemented in Verilog 2001 (IEEE 1365.) The synthesis design code is technology independent and was simulated at both RTL and gate level with timing back annotation using ModelSim SE 5.8e and synthesized using both Leonardo Spectrum V2001_1d.45 and Xilinx's XST 6.1i
Starting Page	172
Ending Page	178
File Size	368286
Page Count	7
File Format	PDF
ISBN	0780397266
DOI	10.1109/DTIS.2006.1708684
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-09-05
Publisher Place	Tunisia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Integrated circuit synthesis Protocols Communication system control Very large scale integration Master-slave Control systems Transceivers Software standards Application software Digital filters
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

VLSI signal generation in echo canceler transceiver

A VLSI implementation of a universal programmable low sensitivity sampled data filter

CAD Tools for the optimized design of custom VLSI wave digital filters

A VLSI architecture of G.SHDSL transceiver

A VLSI implementation of a 3Gb/s LVDS transceiver in CMOS technology

Logic implementation for VLSI

Change Diagram : A behavioural model for very speed VLSI circuit/highly parallel systems

Implementation of High Peak-Current IGBT Gate-Drive Circuits in a VLSI Compatible BiCMOS Technology

On VLSI array architectures for digital image processing

Universal low/medium speed I/sup 2/C-slave transceiver: a detailed VLSI implementation

Similar Documents

VLSI signal generation in echo canceler transceiver

A VLSI implementation of a universal programmable low sensitivity sampled data filter

CAD Tools for the optimized design of custom VLSI wave digital filters

A VLSI architecture of G.SHDSL transceiver

A VLSI implementation of a 3Gb/s LVDS transceiver in CMOS technology

Logic implementation for VLSI

Change Diagram : A behavioural model for very speed VLSI circuit/highly parallel systems

Implementation of High Peak-Current IGBT Gate-Drive Circuits in a VLSI Compatible BiCMOS Technology

On VLSI array architectures for digital image processing

Universal low/medium speed I/sup 2/C-slave transceiver: a detailed VLSI implementation