NDLI: SRAM dedicated PCMs for leakage characterization in nanometer CMOS technologies

Content Provider	IEEE Xplore Digital Library
Author	Leomant, S. Turier, A. Ben Ammar, L. Amara, A.
Copyright Year	2006
Description	Author affiliation: ISEP, Paris (Leomant, S.)
Abstract	Leakage currents are of major concern in nanometer technologies. To address this issue, it is essential to have a good understanding of all leakage contributors, very soon during the new technology development step. This paper presents our methodology to accurately characterize leakage in SRAM cells, while keeping same environment of a product. Process control monitors, containing different structures to measure sub-threshold, gate, gate induced drain and junction leakages, in each SRAM bit-cell transistor, are described. Other structures are used to quantify the impact on leakage of edge effects and strap locations. Presented design and measurement methodology allows a separate characterizing of each leakage contributor; in order to optimize consumption in chips using ATMKL 130nm CMOS technology
Starting Page	316
Ending Page	321
File Size	871562
Page Count	6
File Format	PDF
ISBN	0780397266
DOI	10.1109/DTIS.2006.1708680
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-09-05
Publisher Place	Tunisia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Phase change materials Semiconductor device modeling Semiconductor device measurement Design methodology Random access memory Process control Production CMOS technology Leakage current Design optimization
Content Type	Text
Resource Type	Article

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