NDLI: On the modeling and testing of gate oxide shorts in CMOS logic gates

Content Provider	IEEE Xplore Digital Library
Author	Hong Hao McCluskey, E.J.
Copyright Year	1991
Description	Author affiliation: Center for Reliable Comput., Stanford Univ., CA, USA (Hong Hao; McCluskey, E.J.)
Abstract	The electrical and logic operation of CMOS simple logic gates in the presence of gate oxide shorts is analyzed using realistic defect models. These models reflect the resistive nature of gate oxide shorts and the difference between n- and p-channel transistors. The resistance of a short plays a central role in determining the actual circuit behavior. Faults caused by gate oxide shorts can be dependent not only on inputs to the gate containing the fault but also on other signals in the circuit, and can escape tests generated using normal TPG schemes. The stuck-at test set for a logic gate cannot guarantee to detect all transistor gate-to-source and gate-to-drain shorts in the logic gate. Gate oxide shorts in n-channel transistors affect circuit operation more severely than those in p-channel transistors do. Some limitations of present transistor-level fault modeling techniques are revealed.<>
Starting Page	161
Ending Page	174
File Size	705029
Page Count	14
File Format	PDF
ISBN	0818624574
DOI	10.1109/DFTVS.1991.199958
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1991-11-18
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic testing CMOS logic circuits Semiconductor device modeling Logic gates Circuit faults Circuit testing Voltage CMOS process Switches Logic circuits
Content Type	Text
Resource Type	Article

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