NDLI: Two-pattern generation based on accumulators with 1's complement adders

Content Provider	IEEE Xplore Digital Library
Author	Voyiatzis, I. Efstathiou, C.
Copyright Year	2006
Description	Author affiliation: Technol. Educational Inst. of Athens (Voyiatzis, I.)
Abstract	Built-in self test (BIST) techniques are widely used in today's complex integrated circuits, since they employ on-chip test pattern generation and response verification. Arithmetic BIST techniques utilize modules that commonly exist in datapath modules (accumulators, counters etc.). In order to perform the test generation and response verification operations. In order to detect sequential faults that occur into current CMOS circuits, two-pattern tests are required. Furthermore, delay testing, commonly used to assure correct temporal circuit operation at clock speed, requires two-pattern tests. In this paper a novel algorithm for the generation of two-pattern tests is presented. The presented algorithm utilizes modules included in datapath circuitry to generate two-pattern tests; its implementation in hardware compares favorably with techniques that have been presented in the open literature
Starting Page	365
Ending Page	369
File Size	276049
Page Count	5
File Format	PDF
ISBN	0780397266
DOI	10.1109/DTIS.2006.1708660
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-09-05
Publisher Place	Tunisia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Performance evaluation Automatic testing Integrated circuit testing Built-in self-test Electrical fault detection Test pattern generators Circuit testing Adders Arithmetic Counting circuits
Content Type	Text
Resource Type	Article

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