NDLI: Exploring multistage interconnection network implementations for FPGA-based MPSOCs

Content Provider	IEEE Xplore Digital Library
Author	Aydi, Y. Tligue, R. Abid, M. Dekeyser, J.-L.
Copyright Year	2009
Description	Author affiliation: CES Laboratory, National Engineering School of Sfax (Aydi, Y.; Tligue, R.; Abid, M.) \|\| LIFL and INRIA-Lille, University of Lille, France (Dekeyser, J.-L.)
Abstract	Modern embedded systems integrated a variety of complex and heterogeneous components communicating with each other at high-speed rates. The interconnection architecture employed in such systems has an important impact to their overall performance. Multistage interconnection network has emerged as a promising alternative to ensure communication for Multi Processor System on Chips. In this paper, we describe a design methodology of MIN-based MPSoC on programmable circuits (FPGAs). As a case study, we propose an evaluation methodology based on performance metrics that include latency, execution time and area requirements for two MIN-based MPSOC topologies, i.e. the Omega and the Butterfly Fat Tree (BFT). Moreover, we show in our experimental results that multistage interconnection networks will become a future general purpose interconnect for FPGA-based MPSOCs much like today's standard bus architectures.
Starting Page	1
Ending Page	6
File Size	885039
Page Count	6
File Format	PDF
ISBN	9781424457489
e-ISBN	9781424457502
DOI	10.1109/IDT.2009.5404107
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-11-15
Publisher Place	Saudi Arabia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Measurement Programmable circuits Multiprocessor interconnection networks Design methodology Embedded system Network-on-a-chip Integrated circuit interconnections System-on-a-chip Field programmable gate arrays Multiprocessing systems
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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