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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Cheng, K. |
| Copyright Year | 2010 |
| Description | Author affiliation: Innotest Inc., 2F, 13 R&D Road 1, Science Park, Hsinchu, Taiwan (Cheng, K.) |
| Abstract | Testing a 3-D IC circuitry could be a nightmare, if it is not planned properly. IC testing is always the major part of the manufacturing process. How to cut down the testing cost becomes the most important cost effective issue. In order to reduce the cost of testing the 3-D IC, the boundary scan and redundancy technologies implemented with the 3-D IC design maybe the good approach. 3-D parallel processor and 3-D Computer will be the ultimate architecture of the 3-D IC. No PCB no package and even no cable connector are needed in a 3-D Computer. It also has the benefit of small size light weight high speed and less power consumption to meet the global warming regulation. By the year of 2014 all the IC components will be 3-D architecture. Shortly after that all the PC, cell phone, PDA etc. will be 3-D too. In the next few years the IC and PC industry revolution is going to take place. In this paper a very detail test analysis and strategy will be presented not only for 3-D IC but for the 3-D processor and 3-D Computer. |
| Starting Page | 1 |
| Ending Page | 4 |
| File Size | 2085748 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781424497836 |
| ISSN | 21505942 |
| e-ISBN | 9781424497867 |
| e-ISBN | 9781424497850 |
| DOI | 10.1109/IMPACT.2010.5699538 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2010-10-20 |
| Publisher Place | Taiwan |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Integrated circuits Roads Electronic mail |
| Content Type | Text |
| Resource Type | Article |
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