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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Gurumurthy, K.S. Prahalad, M.S. |
| Copyright Year | 2010 |
| Description | Author affiliation: DOS in Electronics and Communication Engineering, UVCE Bangalore - 560 001, India (Gurumurthy, K.S.; Prahalad, M.S.) |
| Abstract | This paper discusses about "Array of Array" multiplier which is a derivative of Braun Array Multiplier. Braun array are much suitable for VLSI implementation because of its less space complexity though it shows larger time complexity, on the other hand tree multipliers have time complexity of O(log n) but are less suitable for VLSI implementation since, being less regular; they require larger total routing length, which leads to performance degradation; simply put, they show higher space complexity. The main advantage of "Array of Array" multipliers is its inherent ability to reduce both time and space complexity [7] [8] with intermediate relative performance [7]. In this paper a 16×16 unsigned 'Array of Array' multiplier circuit is designed with hierarchical structuring, it has been optimized using Vedic Multiplication Sutra (Algorithm) "Urdhva Triyagbhyam" [1][6] and Karatsuba-Ofman algorithm[2]. The proposed algorithm is useful for math coprocessors in the field of computers. Algorithm is implemented on SPARTAN-3E FPGA (Field Programmable Gate Array). The proposed multiplier implementation shows large reduction in average power dissipation and in time delay as compared to Booth encoded radix-4 multiplier. |
| Starting Page | 1 |
| Ending Page | 4 |
| File Size | 170791 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781424497836 |
| ISSN | 21505942 |
| e-ISBN | 9781424497867 |
| e-ISBN | 9781424497850 |
| DOI | 10.1109/IMPACT.2010.5699463 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2010-10-20 |
| Publisher Place | Taiwan |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Algorithm design and analysis Vedic Mathematics Booth encoded radix-4 multiplier Braun array Urdhva Triyakbhyam Sutra Signal processing algorithms Very large scale integration Complexity theory Arrays Field programmable gate arrays Karatsuba — Ofman algorithm |
| Content Type | Text |
| Resource Type | Article |
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