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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Chang-Chun Lee Tsung-Fu Yang Kuo-Shu Kao Ren-Chin Cheng Chau-Jie Zhan Tai-Hong Chen |
| Copyright Year | 2012 |
| Description | Author affiliation: Department of Mechanical Engineering, Chung Yuan Christian University, 200, Chungpei Rd., Chungli City, Taoyuan County 32023, Taiwan, R.O.C. (Chang-Chun Lee) || Assembly and Reliability Technology Department, Electronics and Optoelectronics Research Laboratories, Industrial Technology Research Institute, 195 Sec. 4, Chung-Hsing Road, Chutung, Hsinchu 31040, Taiwan, R.O.C. (Kuo-Shu Kao; Ren-Chin Cheng; Chau-Jie Zhan; Tai-Hong Chen) || Electronics division, Business Group III, Topco Scientific Co., LTD., 195 Sec. 4, Chung-Hsing Road, Chutung, Hsinchu 31040, Taiwan, R.O.C. (Tsung-Fu Yang) |
| Abstract | Three-dimension (3D) integration provides a promising approach to build complex microsystems through bonding and interconnection of individually optimized device layers without sacrificing system performance. The use of traditional underfill processes is expected to suffer an arduous challenge as the filled gap of a large scale chip is narrowed down to several micrometers. Consequently, the subsequent reliability of mirobump joints and the relative assembly compatibility of stacked chips of 3D integrated circuits (ICs) packages are therefore deteriorated. To resolve the foregoing critical issue, a novel technology of wafer-level underfill film (WLUF) is developed. The concerned steps like alignment of WLUF coated chip to substrate chip and voids elimination to make this technology work are demonstrated. However, the co-planarity of stacked thin chips after assembling with WLUF is an urgent problem and needs to understand in detail. For this reason, this research presents a non-linear finite element analysis (FEA) with process-oriented simulated technique to estimate the warpage of stacked thin chips. On account of experimental validation, the effects of several key designed factors on the thermo-mechanical behavior of chip-on-chip package under various bonding forces are investigated. The most important findings from analytic results indicate that with a consideration of chip thickness thinner than 50µm at the outermost region of packaging structure without microbumps, a about 2µm of gap betweens chips is significantly reduced. The above-mentioned phenomenon is attributed to a major structural support at the purlieus of chip only come from WLUF is extremely weak when a uniform bonding pressures is loaded. It is also found that the following cooling procedure of WLUF would further aggravate the warpage magnitude of stacked thin chips. All the results shown in the work could be as a guideline while the bonding reliability as well as the design of structural optimization for packaging assemblies with WLUF is further improved. |
| Starting Page | 385 |
| Ending Page | 391 |
| File Size | 836423 |
| Page Count | 7 |
| File Format | |
| ISBN | 9781424495337 |
| ISSN | 10879870 |
| e-ISBN | 9781424495320 |
| e-ISBN | 9781424495313 |
| DOI | 10.1109/ITHERM.2012.6231455 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2012-05-30 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Packaging Stress Strain Finite element methods Materials Reliability Bonding 3D ICs Underfill bonding process Microbumps Warpage FEA |
| Content Type | Text |
| Resource Type | Article |
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