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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Xiaoxin Fan Huaxing Tang Reddy, S.M. Wu-Tung Cheng Benware, B. |
| Copyright Year | 2011 |
| Abstract | Recently statistical yield learning based on volume diagnosis has become popular. Volume diagnosis requires a large amount of diagnosis results to be produced within a reasonable time. However, it is challenging to achieve the desired throughput for modern designs with continuously increasing size. In this paper, we propose a method to partition a design under diagnosis into blocks together with a diagnosis flow at the block level. The diagnosis throughput is improved because more diagnosis jobs can be run concurrently and each job runs faster due to the reduced memory. A measure is also proposed to estimate the impact on diagnosis caused by design partitioning. Experimental results on benchmark circuits and several industrial designs show that diagnosis using circuit blocks has minimal impact on diagnosis accuracy and resolution. It is also demonstrated that the proposed measure is a good metric in predicting the impact on diagnosis. |
| Starting Page | 219 |
| Ending Page | 225 |
| File Size | 265371 |
| Page Count | 7 |
| File Format | |
| ISBN | 9781457719844 |
| ISSN | 10817735 |
| DOI | 10.1109/ATS.2011.45 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2011-11-20 |
| Publisher Place | India |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Logic gates Circuit faults Partitioning algorithms Algorithm design and analysis Dictionaries Bismuth Accuracy logic diagnosis yield learning volume diagnosis design partitioning |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electrical and Electronic Engineering |
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