NDLI: Design of a Test Processor for Asynchronous Chip Test

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Table of Contents

Message from General Co-chairs

Message from Technical Program Co-chairs

Program Committee

Steering Committee

On Detecting Transition Faults in the Presence of Clock Delay Faults

Testing of Clock-Domain Crossing Faults in Multi-core System-on-Chip

On-Chip Programmable Dual-Capture for Double Data Rate Interface Timing Test

Time Domain Characterization and Test of High Speed Signals Using Incoherent Sub-sampling

Temperature Dependent Test Scheduling for Multi-core System-on-Chip

Test Scheduling for Multicore SoCs with Dynamic Voltage Scaling and Multiple Voltage Islands

Selective Test Response Collection for Low-Power Scan Testing with Well-Compressed Test Data

Low Power Test-Compression for High Test-Quality and Low Test-Data Volume

Multi-cycle Test with Partial Observation on Scan-Based BIST Structure

SSTKR: Secure and Testable Scan Design through Test Key Randomization

An Innovative Methodology for Scan Chain Insertion and Analysis at RTL

Adaptation of Standard RT Level BIST Architectures for System Level Communication Testing

Rewind-Support for Peak Capture Power Reduction in Launch-Off-Shift Testing

Low Power Decompressor and PRPG with Constant Value Broadcast

Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-Filling

Virtual Circuit Model for Low Power Scan Testing in Linear Decompressor-Based Compression Environment

Test Pattern Selection for Defect-Aware Test

Efficient SAT-Based Search for Longest Sensitisable Paths

Mapping Transaction Level Faults to Stuck-At Faults in Communication Hardware

On Generation of 1-Detect TDF Pattern Set with Significantly Increased SDD Coverage

Yield-per-Area Optimization for 6T-SRAMs Using an Integrated Approach to Exploit Spares and ECC to Efficiently Combat High Defect and Soft-Error Rates

A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits

A New Architecture to Cross-Fertilize On-Line and Manufacturing Testing

Online Test Macro Scheduling and Assignment in MPSoC Design

Distributed Comparison Test Driven Multiprocessor Speed-Tuning: Targeting Performance Gains under Extreme Process Variations

An Online Mechanism to Verify Datapath Execution Using Existing Resources in Chip Multiprocessors

An Efficient 2-Phase Strategy to Achieve High Branch Coverage

Soft Error Recovery Technique for Multiprocessor SOPC

Wrapper Chain Design for Testing TSVs Minimization in Circuit-Partitioned 3D SoC

Identification of Defective TSVs in Pre-Bond Testing of 3D ICs

A Unified Interconnects Testing Scheme for 3D Integrated Circuits

Cost-Effective TSV Grouping for Yield Improvement of 3D-ICs

Improved Fault Diagnosis for Reversible Circuits

Embedded Test for Highly Accurate Defect Localization

On Using Design Partitioning to Reduce Diagnosis Memory Footprint

Exploring Impact of Faults on Branch Predictors' Power for Diagnosis of Faulty Module

Post-Silicon Timing Validation Method Using Path Delay Measurements

Backward Reasoning with Formal Properties: A Methodology for Bug Isolation on Simulation Traces

Design of a Test Processor for Asynchronous Chip Test

On Generating Vectors for Accurate Post-Silicon Delay Characterization

Predicting Scan Compression IP Configurations for Better QoR

Low Test Data Volume Low Power At-Speed Delay Tests Using Clock-Gating

Test Compression Based on Lossy Image Encoding

Multiscan-based Test Data Compression Using UBI Dictionary and Bitmask

Diagnostic Test of Robust Circuits

An Accurate Timing-Aware Diagnosis Algorithm for Multiple Small Delay Defects

Diagnosis of Multiple Scan-Chain Faults in the Presence of System Logic Defects

Diagnosing Multiple Slow Gates for Performance Tuning in the Face of Extreme Process Variations

A Process Monitor Based Speed Binning and Die Matching Algorithm

Optimized Test Error Detection by Probabilistic Retest Recommendation Models

Adaptive Test Framework for Achieving Target Test Quality at Minimal Cost

A Fault Criticality Evaluation Framework of Digital Systems for Error Tolerant Video Applications

Efficient Use of Unused Spare Columns to Improve Memory Error Correcting Rate

New Fault Detection Algorithm for Multi-level Cell Flash Memroies

A New Test Paradigm for Semiconductor Memories in the Nano-Era

On Defect Oriented Testing for Hybrid CMOS/Memristor Memory

Improving the Accuracy of RF Alternate Test Using Multi-VDD Conditions: Application to Envelope-Based Test of LNAs

On Replacing an RF Test with an Alternative Measurement: Theory and a Case Study

Test and Diagnosis of Analog Circuits Using Moment Generating Functions

Mixed-Signal Fault Equivalence: Search and Evaluation

Efficient BDD-based Fault Simulation in Presence of Unknown Values

Analysis of Resistive Bridge Defect Delay Behavior in the Presence of Process Variation

Automation of 3D-DfT Insertion

MarciaTesta: An Automatic Generator of Test Programs for Microprocessors' Data Caches

Testing for Parasitic Memory Effect in SRAMs

Transient Noise Failures in SRAM Cells: Dynamic Noise Margin Metric

Fault Diagnosis in Memory BIST Environment with Non-march Tests

Characterizing Pattern Dependent Delay Effects in DDR Memory Interfaces

Breaking the Test Application Time Barriers in Compression: Adaptive Scan-Cyclical (AS-C)

Exploiting Free LUT Entries to Mitigate Soft Errors in SRAM-based FPGAs

A Single-Configuration Method for Application-Dependent Testing of SRAM-based FPGA Interconnects

Multi-visit TAMs to Reduce the Post-Bond Test Length of 2.5D-SICs with a Passive Silicon Interposer Base

Physical-Aware Memory BIST Datapath Synthesis: Architecture and Case-Studies on Complex SoCs

Failure Analysis and Test Solutions for Low-Power SRAMs

A Robust Solution for Embedded Memory Test and Repair

Nand Flash Memory -- Product Trends, Technology Overview, and Technical Challenges

High Level Verification and Its Use at Pos-Silicon Debugging and Patching

3D Specific Systems: Design and CAD

Testing and Design-for-Testability Techniques for 3D Integrated Circuits

Yield Improvement and Test Cost Optimization for 3D Stacked ICs

Integrated Design & Test: Conquering the Conflicting Requirements of Low-Power, Variation-Tolerance and Test Cost

Dependable VLSI Program in Japan: Program Overview and the Current Status of Dependable VLSI Platform Project

Reliability: A Cross-Disciplinary and Cross-Layer Approach

Underdesigned and Opportunistic Computing

Power Aware Shift and Capture ATPG Methodology for Low Power Designs

Power-Aware Test Pattern Generation for At-Speed LOS Testing

Power Aware Embedded Test

Testability of Cryptographic Hardware and Detection of Hardware Trojans

Test Scheduling in an IEEE P1687 Environment with Resource and Power Constraints

Automatic SoC Level Test Path Synthesis Based on Partial Functional Models

A Boundary Scan Circuit with Time-to-Digital Converter for Delay Testing

Burst-Mode Transmission and Data Recovery for Multi-GHz Optical Packet Switching Network Testing

Publisher's Information

2010 19th IEEE Asian Test Symposium

2009 Asian Test Symposium

2008 17th Asian Test Symposium

16th Asian Test Symposium (ATS 2007)

2006 15th Asian Test Symposium

14th Asian Test Symposium (ATS'05)

13th Asian Test Symposium

2003 Test Symposium

Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).

Proceedings 10th Asian Test Symposium

Proceedings of the Ninth Asian Test Symposium

Proceedings Eighth Asian Test Symposium (ATS'99)

Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259)

Proceedings Sixth Asian Test Symposium (ATS'97)

Proceedings of the Fifth Asian Test Symposium (ATS'96)

Proceedings of the Fourth Asian Test Symposium

Proceedings of IEEE 3rd Asian Test Symposium (ATS)

Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)

Proceedings First Asian Test Symposium (ATS `92)

Design of a Test Processor for Asynchronous Chip Test

Content Provider	IEEE Xplore Digital Library
Author	Zeidler, S. Wolf, C. Krstic, M. Vater, F. Kraemer, R.
Copyright Year	2011
Abstract	Due to asynchronous timing and arbitration asynchronous designs may behave no deterministically. For the test of such systems, this means that an exact timing, i.e. a tester cycle, of a test response cannot be guaranteed. This behavior makes functional tests of asynchronous designs relatively complex or even impossible. Therefore, this paper presents a concept for performing functional tests of asynchronous designs using a test processor infrastructure. To this end, we propose a low-cost 16-bit microprocessor solution with special support of asynchronous handshake signalling that can either be integrated into the device-under-test (DUT), mounted on the load board of the tester or a combination of both.
Starting Page	244
Ending Page	250
File Size	262197
Page Count	7
File Format	PDF
ISBN	9781457719844
ISSN	10817735
DOI	10.1109/ATS.2011.17
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-11-20
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Registers Protocols Pipelines Built-in self-test Synchronization System-on-a-chip timing nondeterminism test processor functional test asynchronous circuits handshake protocols
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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