NDLI: A Unified Interconnects Testing Scheme for 3D Integrated Circuits

Content Provider	IEEE Xplore Digital Library
Author	Chih-Yun Pai Ruei-Ting Cu Bo-Chuan Cheng Liang-Bi Chen Li, K.S.
Copyright Year	2011
Abstract	This paper proposed a full-chip testing scheme for 3D ICs to achieve the integrated horizontal/vertical interconnect reliability and yield enhancement with targets of interconnect faults under stuck-at and open fault models. This scheme is based on our previously developed IEEE std. 1500 compatible oscillation-ring (OR) testing methodology and further applies to Through-Silicon-Vias (TSVs)-based 3D ICs. The experimental results show that the both horizontal and vertical ring generation algorithms can achieve the optimal detectability for any interconnect. Compared with our previous work (IORT) in 2D ICs, the proposed HVOR needs only 43% extra rings for achieving 100% fault coverage in a 2-tier 3D ICs, and this work needs 82% testing time due to the concurrency characteristic in OR test scheme.
Starting Page	195
Ending Page	200
File Size	528850
Page Count	6
File Format	PDF
ISBN	9781457719844
ISSN	10817735
DOI	10.1109/ATS.2011.38
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-11-20
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Three dimensional displays Testing Through-silicon vias Integrated circuit interconnections Circuit faults Oscillators 3D ICs Oscillation ring (OR) test scheme stuck-at faults open faults TSV-based testing
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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