NDLI: Embedded Test for Highly Accurate Defect Localization

Content Provider	IEEE Xplore Digital Library
Author	Mumtaz, A. Imhof, M.E. Holst, S. Wunderlich, H.-J.
Copyright Year	2011
Abstract	Modern diagnosis algorithms are able to identify the defective circuit structure directly from existing fail data without being limited to any specialized fault models. Such algorithms however require test patterns with a high defect coverage, posing a major challenge particularly for embedded testing. In mixed-mode embedded test, a large amount of pseudo-random(PR) patterns are applied prior to deterministic test pattern. Partial Pseudo-Exhaustive Testing (P-PET)replaces these pseudo-random patterns during embedded testing by partial pseudo-exhaustive patterns to test a large portion of a circuit fault-model independently. The overall defect coverage is optimized compared to random testing or deterministic tests using the stuck-at fault model while maintaining a comparable hardware overhead and the same test application time. This work for the first time combines P-PET with a fault model independent diagnosis algorithm and shows that arbitrary defects can be diagnosed on average much more precisely than with standard embedded testing. The results are compared to random pattern testing and deterministic testing targeting stuck-at faults.
Starting Page	213
Ending Page	218
File Size	212607
Page Count	6
File Format	PDF
ISBN	9781457719844
ISSN	10817735
DOI	10.1109/ATS.2011.60
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-11-20
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit faults Logic gates Polynomials Automatic test pattern generation Integrated circuit modeling Signal resolution Debug BIST Pseudo-Exhaustive Testing Diagnosis
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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P-PET: Partial pseudo-exhaustive test for high defect coverage

An intra-cell defect grading tool

A method of one-pass seed generation for LFSR-based deterministic/pseudo-random testing of static faults

Enhancement of Clock Delay Faults Testing

Combining deterministic logic BIST with test point insertion

Combinational test generation for transition faults in acyclic sequential circuits

Improved Fault Diagnosis for Reversible Circuits

Testing IP cores with pseudo exhaustive test sets

Automatic test pattern generation for resistive bridging faults

Embedded Test for Highly Accurate Defect Localization

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P-PET: Partial pseudo-exhaustive test for high defect coverage

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A method of one-pass seed generation for LFSR-based deterministic/pseudo-random testing of static faults

Enhancement of Clock Delay Faults Testing

Combining deterministic logic BIST with test point insertion

Combinational test generation for transition faults in acyclic sequential circuits

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Testing IP cores with pseudo exhaustive test sets

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