NDLI: Register-transfer level fault modeling and test evaluation techniques for VLSI circuits

Content Provider	IEEE Xplore Digital Library
Author	Thaker, P.A. Agrawal, V.D. Zaghloul, M.E.
Copyright Year	2000
Description	Author affiliation: Hughes Network Syst. Inc., Germantown, MD, USA (Thaker, P.A.)
Abstract	Stratified fault sampling is used in RTL fault simulation to estimate the gate-level fault coverage of given test patterns. RTL fault modeling and fault injection algorithm are developed such that the RTL fault list of a module can be treated as a representative fault sample of the collapsed stuck-at fault set of the module. The RTL coverage for the module is experimentally found to track the gate-level coverage within the statistical error bounds. For a VLSI system, consisting of several modules, the overall coverage is a weighted sum of RTL module coverages. Several techniques are proposed to determine these weights, known as stratum weights. For a system timing controller ASIC, the stratified RTL coverage of verification test-benches was estimated within 0.6% of the actual gate-level coverage. This ASIC consists of 40 modules (9,000 lines of Verilog HDL) that are synthesized into 17,126 equivalent logic gates by a commercial synthesis tool. Similar results on two other VLSI systems are reported.
Starting Page	940
Ending Page	949
File Size	932696
Page Count	10
File Format	PDF
ISBN	0780365461
ISSN	10893539
DOI	10.1109/TEST.2000.894305
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-10-05
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit testing Circuit faults Very large scale integration Circuit simulation System testing Application specific integrated circuits Hardware design languages Circuit synthesis Control system synthesis Design for testability
Content Type	Text
Resource Type	Article
Subject	Applied Mathematics Electrical and Electronic Engineering

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