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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Muresan, V. Xiaojun Wang Muresan, V. Vladutiu, M. |
| Copyright Year | 2000 |
| Description | Author affiliation: Dublin City Univ., Ireland (Muresan, V.) |
| Abstract | Classical scheduling approaches are applied here to overcome the problem of unequal-length block-test scheduling under power dissipation constraints. List scheduling-like approaches are proposed first as greedy algorithms to tackle the fore mentioned problem. Then, distribution-graph based approaches are described in order to achieve balanced test concurrency and test power dissipation. An extended tree growing technique is also used in combination with these classical approaches in order to improve the test concurrency having assigned power dissipation limits. A comparison between the results of the test scheduling experiments highlights the advantages and disadvantages of applying different classical scheduling algorithms to the power-constrained test scheduling problem. |
| Starting Page | 882 |
| Ending Page | 891 |
| File Size | 1014212 |
| Page Count | 10 |
| File Format | |
| ISBN | 0780365461 |
| ISSN | 10893539 |
| DOI | 10.1109/TEST.2000.894299 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2000-10-05 |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Circuit testing Power dissipation Concurrent computing System testing Scheduling algorithm Very large scale integration Greedy algorithms Tree graphs Partitioning algorithms Polynomials |
| Content Type | Text |
| Resource Type | Article |
| Subject | Applied Mathematics Electrical and Electronic Engineering |
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