NDLI: Using on-chip test pattern compression for full scan SoC designs

Content Provider	IEEE Xplore Digital Library
Author	Lang, H. Pfeiffer, J. Maguire, J.
Copyright Year	2000
Description	Author affiliation: Motorola Inc., Munich, Germany (Lang, H.)
Abstract	In todays mixed signal System-on-Chip designs advanced Design-for-Test techniques become more and more important to meet test coverage and quality requirements. However, standard strategies often cannot be used because of design specific requirements like the limitation of available input and output pins. This paper describes the Design-for-Test strategy of the latest version of Motorola's chip family for a mixed signal application. Deterministic test pattern, which are generated using an ATPG tool, have been used to stimulate the design and achieve efficient and high test coverage. The memories are tested by using a memory BIST implementation. The limitation of available digital input and output pins is solved in two ways. Analog input pins have been modified to serve as digital pins in test mode. On-chip test pattern compression using a multiple input shift register (MISR) is used to reduce the number of required output pins. Failure diagnostic capabilities have been implemented to allow debug of failing devices. The paper describes the test strategy for the System-on-Chip device and outlines the design flow which was used to implement it.
Starting Page	638
Ending Page	643
File Size	503642
Page Count	6
File Format	PDF
ISBN	0780365461
ISSN	10893539
DOI	10.1109/TEST.2000.894258
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-10-05
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Design for testability Pins System-on-a-chip Automatic testing Signal design Automatic test pattern generation Application specific integrated circuits Logic testing Analog integrated circuits System testing
Content Type	Text
Resource Type	Article
Subject	Applied Mathematics Electrical and Electronic Engineering

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