NDLI: Analysis of interconnect crosstalk defect coverage of test sets

Content Provider	IEEE Xplore Digital Library
Author	Zhao, Y. Dey, S.
Copyright Year	2000
Description	Author affiliation: Dept. of Electr. & Comput. Eng., California Univ., San Diego, La Jolla, CA, USA (Zhao, Y.)
Abstract	This paper addresses the problem of evaluating the effectiveness of test sets to detect crosstalk defects in interconnects of deep sub-micron circuits. The fast and accurate estimation technique will enable: (a) evaluation of different existing tests, like functional, scan, logic BIST, and delay tests, for effective testing of crosstalk defects in interconnects, and (b) development of crosstalk tests if the existing tests are not sufficient, thereby minimizing the cost of interconnect testing. Based on a covering relationship we establish between transition tests in detecting crosstalk defects, we develop an abstract crosstalk fault model for circuit interconnects. Based on this fault model, and the covering relationship, we develop a fast and efficient method to estimate the fault coverage of any general test set. We also develop a simulation-based technique to calculate the probability of occurrence of the defects corresponding to each fault, which enables the fault coverage analysis technique to produce accurate estimates of the actual crosstalk defect coverage of a given test set. The crosstalk test and fault properties, as well as the accuracy of the proposed crosstalk coverage analysis techniques, have been validated through extensive simulation experiments. The experiments also demonstrate that the proposed crosstalk techniques are orders of magnitude faster than the alternative method of SPICE-level simulation. Finally, we demonstrate the practical applicability of the proposed fault coverage analysis technique by using it to evaluate the crosstalk fault coverage of logic BIST tests for the buses in a DSP core.
Starting Page	492
Ending Page	501
File Size	1042316
Page Count	10
File Format	PDF
ISBN	0780365461
ISSN	10893539
DOI	10.1109/TEST.2000.894242
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-10-05
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Crosstalk Circuit testing Logic testing Circuit faults Integrated circuit interconnections Delay estimation Built-in self-test Analytical models Delay effects Cost function
Content Type	Text
Resource Type	Article
Subject	Applied Mathematics Electrical and Electronic Engineering

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