NDLI: Compliant Wafer Level Package for Enhanced Reliability

Content Provider	IEEE Xplore Digital Library
Author	Guilian Gao Haba, B. Oganesian, V. Honer, K. Ovrutsky, D. Rosenstein, C. Axelrod, E. Hazanovich, F. Aksenton, Y.
Copyright Year	2007
Description	Author affiliation: Tessera Inc., San Jose (Guilian Gao; Haba, B.; Oganesian, V.; Honer, K.)
Abstract	Wafer level package (WLP) volumes are steadily increasing due to their small package size and low manufacturing cost. However, applications to date have been mostly limited to die smaller than 5mm x 5mm. Solder joint fatigue due to stresses generated by the CTE mismatch between the die and the printed circuit board (PCB) limits adoption of WLP for large dies. Tessera's new compliant WLP technology greatly enhances thermal fatigue reliability of the package. A compliant layer under the solder joints effectively dissipates thermomechanical stress between the die and the PCB. FEA analysis was carried out to optimize compliant layer shape and mechanical properties, several materials were evaluated for this application, and prototype units were built. The prototype 9mm x 14mm packages exceeded 1600 cycles of temperature cycling from -40 degC to 125 degC. A compliant WLP package version with copper pins was also developed and tested for continuity at the wafer level. This structure has the potential to reduce wafer level test and burn-in (WLBT) costs substantially by eliminating the need for expensive die contact on the whole wafer contactor.
Starting Page	1
Ending Page	5
File Size	1579230
Page Count	5
File Format	PDF
ISBN	1424412528
DOI	10.1109/HDP.2007.4283563
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-06-26
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Wafer scale integration Packaging Costs Soldering Fatigue Thermal stresses Prototypes Testing Manufacturing Printed circuits
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in