NDLI: DRIE, an Enabling Technology for High Density Packaging

Content Provider	IEEE Xplore Digital Library
Author	Lea, L. Barker, L. Hopkins, J.
Copyright Year	2007
Description	Author affiliation: Surface Technol. Syst. plc, Newport (Lea, L.; Barker, L.; Hopkins, J.)
Abstract	Efficient plasma processing equipment that has made possible the cost effective precision etching of MEMS devices, is equally capable of providing very high etch rates and excellent etch uniformity when applied to device packaging requirements. Deep Reactive Ion Etching (DRIE) can be used to etch interconnect vias prior to metallization for System-in-Package (SiP) applications. One such technology focuses on fabricating 3D stacks of chips in a single package. Alternatively, the requirement may be for the etching of scribe channels and the exposure of contacts to devices as an intermediate stage in a Chip Scale Packaging (CSP) process. Many MEMS devices are still etched on 150 mm wafers, while most IC devices requiring CSP or other processing relating to Advanced Packaging will be manufactured on 200 mm wafers with planned moves to 300 mm wafers in progress or imminent. For these requirements it becomes increasingly important to design plasma processing equipment that is capable of achieving very high etch uniformity over the larger wafer sizes and high etch rate to reduce the cost of ownership. Experimental results of direct application to device packaging are presented for wafer sizes up to and including 300 mm, demonstrating the capabilities of the latest technical developments.
Starting Page	1
Ending Page	3
File Size	1647525
Page Count	3
File Format	PDF
ISBN	1424412528
DOI	10.1109/HDP.2007.4283587
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-06-26
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Etching Packaging machines Chip scale packaging Plasma applications Plasma devices Plasma materials processing Costs Microelectromechanical devices Plasma density Metallization
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
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