NDLI: VLSI Implementation of Sub-pixel Interpolator for H.264/AVC Encoder

Content Provider	IEEE Xplore Digital Library
Author	Zhai Haihua Xi Zhiqi Chen Guanghua
Copyright Year	2007
Description	Author affiliation: Key Lab. of Adv. Display & Syst. Applic., Shanghai Univ., Shanghai (Zhai Haihua; Xi Zhiqi; Chen Guanghua)
Abstract	The design of H.264/AVC interpolation unit is very challenging for the high memory bandwidth and large calculation complexity caused by the new coding features of variable block size (VBS) and 6-tap filter. In this paper, a novel one-step interpolation implementation algorithm is proposed which can effectively reduce processing cycle because of its less memory accessing. Moreover, a data reuse scheme is used to save processing cycle and memory bandwidth. A high performance hardware architecture is implemented according to the methods mentioned above. As a result, 26% memory bandwidth reduction and 45% processing cycle reduction are achieved, which shows that our architecture is an efficient hardware accelerating solution and can be used in real-time encoder.
Starting Page	1
Ending Page	3
File Size	439676
Page Count	3
File Format	PDF
ISBN	1424412528
DOI	10.1109/HDP.2007.4283630
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-06-26
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Very large scale integration Automatic voltage control Interpolation Bandwidth Filters Hardware High definition video Computer architecture Laboratories Displays data reuse H.264/AVC one-step interpolation
Content Type	Text
Resource Type	Article

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