NDLI: A Built-In Self-Repair Scheme for Multiport RAMs

Content Provider	IEEE Xplore Digital Library
Author	Tsu-Wei Tseng Chun-Hsien Wu Yu-Jen Huang Jin-Fu Li Pao, A. Chiu, K. Chen, E.
Copyright Year	2007
Description	Author affiliation: Dept. of Electr. Eng., National Central Univ., Jhongli (Tsu-Wei Tseng)
Abstract	Built-in self-repair (BISR) techniques have been widely used for enhancing the yield of embedded memories. This paper presents an efficient BISR scheme for multiport RAMs (MPRAMs). The BISR scheme has a defect-location module (DLM) executing a defect-location algorithm to locate inter-port defects. This enhances the fault-location capability of the applied test algorithm with only a few amount of cost of testing time. A built-in redundancy analyzer (BIRA) executing a proposed redundancy analysis algorithm is also proposed to allocate two-dimension redundancy of MPRAMs. Experimental results show that if a faulty MPRAM has 20% inter-port faults, the DLM can boost the increment of repair rate from 8.4% to 14.4% for different redundancy configurations. The area cost of the BIRA and DLM is small, it is only about 1% for a 4096 times 128-bit MPRAM with 1 spare row and 1 spare IO.
Starting Page	355
Ending Page	360
File Size	147269
Page Count	6
File Format	PDF
ISBN	0769528120
ISSN	10930167
DOI	10.1109/VTS.2007.4
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-05-06
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Redundancy Testing Algorithm design and analysis Random access memory NP-complete problem Hardware Cost function Heuristic algorithms Error correction codes Built-in self-test
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A Reconfigurable Built-In Self-Repair Scheme for Multiple Repairable RAMs in SOCs

Efficient built in self repair techniques for repairing multiport embedded RAMs

A Sharable Built-in Self-repair for Semiconductor Memories with 2-D Redundancy Scheme

A built-in self-repair design for RAMs with 2-D redundancy

A Low-Cost Built-In Redundancy-Analysis Scheme for Word-Oriented RAMs With 2-D Redundancy

High Repair-Efficiency BISR Scheme for RAMs by Reusing Bitmap for Bit Redundancy

Cost-Efficient Built-In Redundancy Analysis With Optimal Repair Rate for RAMs

ReBISR: A Reconfigurable Built-In Self-Repair Scheme for Random Access Memories in SOCs

Test and Repair Scheduling for Built-In Self-Repair RAMs in SOCs

A Built-In Self-Repair Scheme for Multiport RAMs

Similar Documents

A Reconfigurable Built-In Self-Repair Scheme for Multiple Repairable RAMs in SOCs

Efficient built in self repair techniques for repairing multiport embedded RAMs

A Sharable Built-in Self-repair for Semiconductor Memories with 2-D Redundancy Scheme

A built-in self-repair design for RAMs with 2-D redundancy

A Low-Cost Built-In Redundancy-Analysis Scheme for Word-Oriented RAMs With 2-D Redundancy

High Repair-Efficiency BISR Scheme for RAMs by Reusing Bitmap for Bit Redundancy

Cost-Efficient Built-In Redundancy Analysis With Optimal Repair Rate for RAMs

ReBISR: A Reconfigurable Built-In Self-Repair Scheme for Random Access Memories in SOCs

Test and Repair Scheduling for Built-In Self-Repair RAMs in SOCs

A Built-In Self-Repair Scheme for Multiport RAMs