NDLI: Circuit Failure Prediction and Its Application to Transistor Aging

Content Provider	IEEE Xplore Digital Library
Author	Agarwal, M. Paul, B.C. Ming Zhang Mitra, S.
Copyright Year	2007
Description	Author affiliation: Stanford Univ., CA (Agarwal, M.)
Abstract	Circuit failure prediction predicts the occurrence of a circuit failure before errors actually appear in system data and states. This is in contrast to classical error detection where a failure is detected after errors appear in system data and states. Circuit failure prediction is performed during system operation by analyzing the data collected by sensors inserted at various locations inside a chip. We demonstrate this concept of circuit failure prediction for a dominant PMOS aging mechanism induced by negative bias temperature instability (NBTI). NBTI-induced PMOS aging slows down PMOS transistors over time. As a result, the speed of a chip can significantly degrade over time and can result in delay faults. The traditional practice is to incorporate worst-case speed margins to prevent delay faults during system operation due to NBTI aging. A new sensor design integrated inside a flip-flop enables efficient circuit failure prediction at a low cost. Simulation results using 90nm and 65nm technologies demonstrate that this technique can significantly improve system performance by enabling close to best-case design instead of traditional worst-case design.
Starting Page	277
Ending Page	286
File Size	364406
Page Count	10
File Format	PDF
ISBN	0769528120
ISSN	10930167
DOI	10.1109/VTS.2007.22
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-05-06
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Aging Niobium compounds Titanium compounds Circuit faults Data analysis Failure analysis Performance analysis Sensor systems Negative bias temperature instability MOSFETs
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Circuit Failure Prediction Enables Robust System Design Resilient to Aging and Wearout

On the efficacy of input Vector Control to mitigate NBTI effects and leakage power

Impact of negative bias temperature instability on product parametric drift

Negative bias temperature instability in triple gate transistors

NBTI-Aware Synthesis of Digital Circuits

Towards Understanding Negative Bias Temperature Instability

Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI

An Approach to Detect Negative Bias Temperature Instability (NBTI) in Ultra-Deep Submicron Technologies

Adaptive techniques for overcoming performance degradation due to aging in digital circuits

Circuit Failure Prediction and Its Application to Transistor Aging

Similar Documents

Circuit Failure Prediction Enables Robust System Design Resilient to Aging and Wearout

On the efficacy of input Vector Control to mitigate NBTI effects and leakage power

Impact of negative bias temperature instability on product parametric drift

Negative bias temperature instability in triple gate transistors

NBTI-Aware Synthesis of Digital Circuits

Towards Understanding Negative Bias Temperature Instability

Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI

An Approach to Detect Negative Bias Temperature Instability (NBTI) in Ultra-Deep Submicron Technologies

Adaptive techniques for overcoming performance degradation due to aging in digital circuits

Circuit Failure Prediction and Its Application to Transistor Aging