NDLI: Session Abstract

Please wait, while we are loading the content...

2015 IEEE 33rd VLSI Test Symposium (VTS)

2014 IEEE 32nd VLSI Test Symposium (VTS)

2013 IEEE 31st VLSI Test Symposium (VTS)

2012 IEEE 30th VLSI Test Symposium (VTS)

29th VLSI Test Symposium

2010 28th VLSI Test Symposium (VTS)

2009 27th IEEE VLSI Test Symposium

26th IEEE VLSI Test Symposium (vts 2008)

25th IEEE VLSI Test Symposium (VTS'07)

25th IEEE VLSI Test Symmposium - Title page

25th IEEE VLSI Test Symmposium - Copyright notice

Steering Committee

Program Committee

Acknowledgments

Test Technology Technical Council (TTTC)

Test Technology Educational Program (TTEP) Tutorials

A Low-Cost RF MIMO Test Method Using a Single Measurement Set-up

Non-RF to RF Test Correlation Using Learning Machines: A Case Study

RF Digital Signal Generation Beyond Nyquist

Delay Test Quality Evaluation Using Bounded Gate Delays

On Performance Testing with Path Delay Patterns

Power Virus Generation Using Behavioral Models of Circuits

Session Abstract

Retention and Reliability Problems in Embedded Flash Memories: Analysis and Test of Defective 2T-FLOTOX Tunnel Window

SDRAM Delay Fault Modeling and Performance Testing

Optimizing Test Length for Soft Faults in DRAM Devices

Minimizing the Impact of Scan Compression

Low Power Embedded Deterministic Test

Multimode Illinois Scan Architecture for Test Application Time and Test Data Volume Reduction

Session Abstract

On a New Outlier Rejection Technique

Enhanced Resolution Jitter Testing Using Jitter Expansion

Using Clock-Vdd to Test and Diagnose the Power-Switch in Power-Gating Circuit

A Programmable Window Comparator for Analog Online Testing

Probabilistic Compensation for Digital Filters Using Pervasive Noise-Induced Operator Errors

Error Tolerance in DNA Self-Assembly by (2k-1) x (2k-1) Snake Tile Sets

Session Abstract

Diagnosis of Bridging Defects Based on Current Signatures at Low Power Supply Voltages

Handling Pattern-Dependent Delay Faults in Diagnosis

Diagnosis of Full Open Defects in Interconnecting Lines

Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test

An Integrated Framework for At-Speed and ATE-Driven Delay Test of Contract-Manufactured ASICs

Supply Voltage Noise Aware ATPG for Transition Delay Faults

Session Abstract

Session Abstract

Session Abstract

Test Set Reordering Using the Gate Exhaustive Test Metric

An Analysis of Defect Detection for Weighted Random Patterns Generated with Observation/Excitation-Aware Partial Fault Targeting

Using Multiple Expansion Ratios and Dependency Analysis to Improve Test Compression

Accelerating Diagnosis via Dominance Relations between Sets of Faults

Speeding Up Effect-Cause Defect Diagnosis Using a Small Dictionary

Using Scan-Dump Values to Improve Functional-Diagnosis Methodology

Session Abstract

A UML Based System Level Failure Rate Assessment Technique for SoC Designs

An Analysis Framework for Transient-Error Tolerance

Case Study: Soft Error Rate Analysis in Storage Systems

Silicon Evaluation of Static Alternative Fault Models

Parameter Estimation for a Model with Both Imperfect Test and Repair

Circuit Failure Prediction and Its Application to Transistor Aging

Session Abstract

Transformer-Coupled Loopback Test for Differential Mixed-Signal Specifications

Novel Cross-Loopback Based Test Approach for Specification Test of Multi-Band, Multi-Hardware Radios

Code-Density Test of Analog-to-Digital Converters Using Single Low-Linearity Stimulus Signal

High Level Synthesis of Degradable ASICs Using Virtual Binding

Efficient RTL Coverage Metric for Functional Test Selection

RTL Test Point Insertion to Reduce Delay Test Volume

Session Abstract

Session Abstract

Session Abstract

Session Abstract

Multiple Bit Upset Tolerant Memory Using a Selective Cycle Avoidance Based SEC-DED-DAEC Code

A Built-In Self-Repair Scheme for Multiport RAMs

Un-Restored Destructive Write Faults Due to Resistive-Open Defects in the Write Driver of SRAMs

Using Domain Partitioning in Wrapper Design for IP Cores Under Power Constraints

Design of Test Access Mechanism for AMBA-Based System-on-a-Chip

TAM Design and Optimization for Transparency-Based SoC Test

A Low Cost Spectral Power Extraction Technique for RF Transceiver Testing

Alternate Diagnostic Testing and Compensation of RF Transmitter Performance Using Response Detection

A Low-Noise Amplifier with Integrated Current and Power Sensors for RF BIST Applications

Automated Design and Insertion of Optimal One-Hot Bus Encoders

Autoscan-Invert: An Improved Scan Design without External Scan Inputs or Outputs

Transition Fault Testability in Bit Parallel Multipliers over GF(2^{m})

Session Abstract

DfT for the Reuse of Networks-on-Chip as Test Access Mechanism

Novel Approach to Clock Fault Testing for High Performance Microprocessors

At-Speed Testing of Core-Based System-on-Chip Using an Embedded Micro-Tester

VIm-Scan: A Low Overhead Scan Design Approach for Protection of Secret Key in Scan-Based Secure Chips

Effects of Embedded Decompression and Compaction Architectures on Side-Channel Attack Resistance

Session Abstract

Session Abstract

Session Abstract

Session Abstract

24th IEEE VLSI Test Symposium

23rd IEEE VLSI Test Symposium (VTS'05)

22nd IEEE VLSI Test Symposium, 2004. Proceedings.

Proceedings. 21st VLSI Test Symposium, 2003.

Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)

Proceedings 19th IEEE VLSI Test Symposium. VTS 2001

Proceedings 18th IEEE VLSI Test Symposium

Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)

Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)

Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125)

Proceedings of 14th VLSI Test Symposium

Proceedings 13th IEEE VLSI Test Symposium

Proceedings of IEEE VLSI Test Symposium

Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium

Digest of Papers. 1992 IEEE VLSI Test Symposium

Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in