NDLI: On Performance Testing with Path Delay Patterns

Content Provider	IEEE Xplore Digital Library
Author	Kruseman, B. Majhi, A. Gronthoud, G.
Copyright Year	2007
Description	Author affiliation: NXP Semicond., Eindhoven (Kruseman, B.; Majhi, A.; Gronthoud, G.)
Abstract	Application specific ICs are typically designed to meet a given performance specification. For these ICs a higher performance does not add value and less performance makes the IC useless. This class of ICs is designed based on worst-case corner analysis. It is expected that this will become area costly in more advanced technologies. An alternative is to use statistical design techniques but this implies that the performance needs to be tested with, for example, path delay testing. Our experiments in 65 nm show that the actual delay depends on the global activity within an IC as well as effects in the local neighbourhood of the path. These global and local effects can independently cause about 15% of additional delay. Hence, their impact needs to be included during test and thr authors propose to create (close to) worst-case delay patterns. Individually, the patterns have an enhanced sensitivity for the most important local effects and combined they provide coverage for global effects. This makes them better suited as speed indicators than conventional path delay patterns.
Starting Page	29
Ending Page	34
File Size	259232
Page Count	6
File Format	PDF
ISBN	0769528120
ISSN	10930167
DOI	10.1109/VTS.2007.45
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-05-06
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Frequency Libraries Delay effects Costs Added delay Performance analysis Ring oscillators Test pattern generators Electronic equipment testing Consumer electronics
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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