NDLI: Probabilistic Compensation for Digital Filters Using Pervasive Noise-Induced Operator Errors

Content Provider	IEEE Xplore Digital Library
Author	Ashouei, M. Bhattacharya, S. Chatterjee, A.
Copyright Year	2007
Description	Author affiliation: Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA (Ashouei, M.; Bhattacharya, S.; Chatterjee, A.)
Abstract	It is well known that scaled CMOS technologies are increasingly susceptible to induced soft errors and environmental noise. Probabilistic checksum-based error detection and compensation has been proposed in the past for scaled DSP circuits for which a certain level of inaccuracy can be tolerated as long as system-level quality-of-service (QoS) metrics are satisfied. Although the technique has been shown to be effective in improving the SNR of digital filters, it can only handle errors that occur in the system states. However, the transient-error rate of combinational logic is increasing with technology scaling. Therefore, handling errors in the arithmetic logic circuitry of DSP systems is also essential. This is a significantly more difficult task due to the fact that a single error at the output of an adder or multiplier can propagate to more than one system state causing multiple states to be erroneous. In this paper, a unified scheme that can address probabilistic compensation for errors both in the system states and in the embedded adders and multipliers of DSP filters is developed. It is shown that by careful checksum code design, significant SNR improvements (up to 13 dB) can be obtained for linear filters in the presence of soft errors.
Starting Page	125
Ending Page	130
File Size	375401
Page Count	6
File Format	PDF
ISBN	0769528120
ISSN	10930167
DOI	10.1109/VTS.2007.50
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-05-06
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Digital filters Digital signal processing Working environment noise CMOS technology Adders Nonlinear filters Circuit noise Quality of service Signal to noise ratio Logic
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Probabilistic Compensation for Digital Filters under Pervasive Noise-Induced Operator Errors, accepted (2007)

Probabilistic Concurrent Error Compensation in Nonlinear Digital Filters Using Linearized Checksums

High Speed CMOS Adder and Multiplier Modules for Digital Signal Processing in a Semicustom Environment

A More Precise Model of Noise Based PCMOS Errors

1.047GHz, 1.2V, 90nm CMOS, 2-Way VLIW DSP Core Using Saturation Anticipator Circuit

The impact of induced gate noise when simultaneously power and conjugate noise-matching MOS transistors

CMOS Digital Signal-Processing Codec Filter with High Performance and Flexibility

Robust high-performance low-power carry select adder

Simplified Low-Voltage CMOS Syllabic Companding Log Domain Filter

Probabilistic Compensation for Digital Filters Using Pervasive Noise-Induced Operator Errors

Similar Documents

Probabilistic Compensation for Digital Filters under Pervasive Noise-Induced Operator Errors, accepted (2007)

Probabilistic Concurrent Error Compensation in Nonlinear Digital Filters Using Linearized Checksums

High Speed CMOS Adder and Multiplier Modules for Digital Signal Processing in a Semicustom Environment

A More Precise Model of Noise Based PCMOS Errors

1.047GHz, 1.2V, 90nm CMOS, 2-Way VLIW DSP Core Using Saturation Anticipator Circuit

The impact of induced gate noise when simultaneously power and conjugate noise-matching MOS transistors

CMOS Digital Signal-Processing Codec Filter with High Performance and Flexibility

Robust high-performance low-power carry select adder

Simplified Low-Voltage CMOS Syllabic Companding Log Domain Filter

Probabilistic Compensation for Digital Filters Using Pervasive Noise-Induced Operator Errors