NDLI: Soft delay error effects in CMOS combinational circuits

Content Provider	IEEE Xplore Digital Library
Author	Gill, B.S. Papachristou, C. Wolff, F.G.
Copyright Year	2004
Description	Author affiliation: Dept. of Electr. Eng. & Comput. Sci., Case Western Reserve Univ., Cleveland, OH, USA (Gill, B.S.; Papachristou, C.; Wolff, F.G.)
Abstract	Single event upsets (SEUs) are due to high energetic particle strike at sensitive nodes of CMOS combinational circuits. In this paper, we introduce a type of soft errors which manifests as soft delay. The soft delay is temporary delay in CMOS combinational circuits due to high energetic particle strike. We describe soft delay model which enables us to examine delay in CMOS combinational circuits due to particle strike. As technology scales down, the delay due to particle strike increases, and other factors such as V/sub dd/ scaling, fanout and transistor strength also contribute to increase the soft delay in CMOS combinational circuits.
Sponsorship	IEEE Comput. Soc. Test Technol. Tech. Council
Starting Page	325
Ending Page	330
File Size	1452354
Page Count	6
File Format	PDF
ISBN	0769521347
ISSN	10930167
DOI	10.1109/VTEST.2004.1299260
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-04-25
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Delay effects Combinational circuits Single event transient CMOS logic circuits CMOS technology Semiconductor device modeling Single event upset Computer errors Error analysis Alpha particles
Content Type	Text
Resource Type	Article

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