NDLI: A scalable on-chip jitter extraction technique

Content Provider	IEEE Xplore Digital Library
Author	Chee-Kian Ong Dongwoo Hong Kwang-Ting Cheng Wang, L.-C.
Copyright Year	2004
Description	Author affiliation: Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA (Chee-Kian Ong; Dongwoo Hong; Kwang-Ting Cheng; Wang, L.-C.)
Abstract	In this paper, we propose a method for extracting the spectral information of a multi-gigahertz jittery signal. This method utilizes existing on-chip single-shot period measurement techniques to sample and measure the period of multiple cycles of the multi-gigahertz periodic signal for spectral analysis. Since measurements are made on the period of multiple cycles, but not on the period of a single cycle, a lower-speed timing measurement circuitry can be used to measure a higher-speed signal. Therefore, the proposed solution is scalable for even higher-speed signals. This method does not require an external sampling clock, nor any additional measurement beyond existing techniques. Experimental results based on simulation show that this method can accurately estimate the sinusoidal and random jitters of a multi-gigahertz signal.
Sponsorship	IEEE Comput. Soc. Test Technol. Tech. Council
Starting Page	267
Ending Page	272
File Size	1488458
Page Count	6
File Format	PDF
ISBN	0769521347
ISSN	10930167
DOI	10.1109/VTEST.2004.1299253
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-04-25
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Jitter Testing Timing Data mining Spectral analysis Clocks Signal processing Frequency Circuits Reliability engineering
Content Type	Text
Resource Type	Article

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