NDLI: Memory BIST using ESP

Content Provider	IEEE Xplore Digital Library
Author	Xiaogang Du Reddy, S.M. Ross, D.E. Wu-Tung Cheng Rayhawk, J.
Copyright Year	2004
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA (Xiaogang Du; Reddy, S.M.)
Abstract	A memory BIST enhancement, ESP short for exercising system paths, is described that allows the efficiency and functional capabilities of standard approaches while addressing two important problems. Conventional Memory BIST techniques require MUXes at the inputs of the memory that allow for the inputs to be driven either by system signals or by test signals. These MUXes add delays, in the system path going to the memory, which often has critical timing. ESP eliminates such delays by implementing the MUXing function 'before' scan cells. ESP also uses scan cells to capture the memory output for feeding back to the BIST controller. This output may have traveled through some logic before getting to the recording scan cells. By including the delays of the system input and output paths, ESP allows for verifying that the memory will work correctly as part of the system rather than just as an isolated unit. Using ESP, a memory BIST can catch transition and delay faults that are impractical, or even impossible, to catch otherwise. Therefore, ESP can be useful for all memories but may be crucial for the memories which cannot tolerate the addition of the MUX delay to functional paths.
Sponsorship	IEEE Comput. Soc. Test Technol. Tech. Council
Starting Page	243
Ending Page	248
File Size	1350605
Page Count	6
File Format	PDF
ISBN	0769521347
ISSN	10930167
DOI	10.1109/VTEST.2004.1299250
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-04-25
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Built-in self-test Electrostatic precipitators Memory architecture Signal generators Logic testing System testing Delay systems Timing System-on-a-chip Logic arrays
Content Type	Text
Resource Type	Article

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