NDLI: ELF-Murphy data on defects and tests sets

Content Provider	IEEE Xplore Digital Library
Author	McCluskey, E.J. Al-Yamani, A. Li, J.C.-M. Chao-Wen Tseng Volkerink, E. Ferhani, F.-F. Li, E. Mitra, S.
Copyright Year	2004
Abstract	LSI logic has designed and manufactured two test chips at CRC. These test chips were used to investigate the characteristics of actual production defects and the effectiveness of various test techniques in detecting their presence. This paper presents a characterization of the defects that shows that very few defective chips act as if they had a single-stuck fault present and that most of the defects cause sequence-dependent behavior. A variety of techniques are used to reduce the size of test sets for digital chips. They typically rely on preserving the single-stuck-fault coverage of the test set. This strategy doesn't guarantee that the defect coverage is retained. This paper presents data obtained from applying a variety of test sets on two chips (Murphy and ELF35) and recording the test escapes. The reductions in test size can thus be compared with the increases in test escapes. The data shows that, even when the fault coverage is preserved, there is a penalty in test quality. Also presented is the data showing the effect of reducing the fault coverage. Techniques studied include various single-stuck-fault models including inserting faults at the inputs of complex gates such as adders, multiplexers, etc. This technique is compatible with the use of structural RTL netlists. Other techniques presented include compaction techniques and don't care bit assignment strategies.
Sponsorship	IEEE Comput. Soc. Test Technol. Tech. Council
Starting Page	16
Ending Page	22
File Size	1403588
Page Count	7
File Format	PDF
ISBN	0769521347
ISSN	10930167
DOI	10.1109/VTEST.2004.1299220
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-04-25
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic testing Circuit faults Chip scale packaging Chaos Large scale integration Logic design Circuit testing Threshold voltage Classification tree analysis Sun
Content Type	Text
Resource Type	Article

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