NDLI: A highly manufacturable MIPS (metal inserted poly-Si stack) technology with novel threshold voltage control

Content Provider	IEEE Xplore Digital Library
Author	Hyung-Suk Jung Jong-Ho Lee Sung Kee Han Yun-Seok Kim Ha Jin Lim Min Joo Kim Seok Joo Doh Mi Young Yu Nae-In Lee Hye-Lan Lee Taek-Soo Jeon Hag-Ju Cho Sang Bom Kang Sang Yong Kim Im Soo Park Dongchan Kim Hion Suck Baik Young Su Chung
Copyright Year	2005
Description	Author affiliation: Syst. LSI Div., Samsung Electron. Co. Ltd., Kyunggi-Do, South Korea (Hyung-Suk Jung; Jong-Ho Lee; Sung Kee Han; Yun-Seok Kim; Ha Jin Lim; Min Joo Kim; Seok Joo Doh; Mi Young Yu; Nae-In Lee)
Abstract	The novel technique to control the V/sub th/ of n/pMOS for HfSiO(N) in both poly-Si and MIPS (metal inserted poly-Si stack) gates is demonstrated. By adding AlO/sub x/ on HfSiO prior to poly-Si deposition, we successfully achieve symmetrical V/sub th/, values of 0.52V (nMOS), /-0.51V (pMOS) and high performance as I/sub on/, of 423uA/um for nMOS and 207uA/um for pMOS at I/sub off/=20pA/um. In addition, we find out that the ultra-thin and conformal TaN layer in MIPS gate does not contribute to the gate work function. By optimizing the TaN thickness, similar V/sub th/ values, compared to poly-Si gate, are achieved. Consequently, the measured saturation currents at I/sub off/=20pA/um are 430uA/um for nMOS and 250uA/um for pMOS. Both issues of PBTI for HfSiO/AlO/sub x//poly-Si structure and NBTI for HfSiO/AlO/sub x//MIPS structure are resolved by optimizing the post deposition annealing condition and using ozone interfacial oxide, respectively.
Sponsorship	Japan Soc. of Appl. Phys. IEEE Electron Devices Soc
Starting Page	232
Ending Page	233
File Size	451605
Page Count	2
File Format	PDF
ISBN	4900784001
DOI	10.1109/.2005.1469280
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-06-14
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	JSAP
Subject Keyword	Manufacturing Threshold voltage Voltage control Niobium compounds Titanium compounds Degradation MOS devices Very large scale integration High K dielectric materials High-K gate dielectrics
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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