NDLI: Highly scalable and reliable 2-bit/cell SONOS memory transistor beyond 50nm NVM technology using outer sidewall spacer scheme with damascene gate process

Content Provider	IEEE Xplore Digital Library
Author	Byung Yong Choi Byung-Gook Park Yong Kyu Lee Suk Kang Sung Tae Yong Kim Eun Suk Cho Hye Jin Cho Chang Woo Oh Sung Hwan Kim Dong Won Kim Choong-Ho Lee Donggun Park
Copyright Year	2005
Description	Author affiliation: Sch. of Electr. Eng. & Comput. Sci., Seoul Nat. Univ., South Korea (Byung Yong Choi; Byung-Gook Park)
Abstract	We present a 2-bit/cell SONOS memory transistor and investigate its scalability and reliability beyond 50nm NVM technology. This new memory, which is implemented by the damascene gate and our newly developed outer sidewall spacer processes, shows not only stable 2-bit operation but also high reliabilities (>10/sup 5/ endurance and good retention at 150/spl deg/C) down to 80nm gate length that applies to next-generation NVM technology. In addition, dimensional effect (the lateral distance between two storage nodes) on the memory operation is reported to estimate the ultimate scaling limit of 2-bit/cell SONOS memory transistor.
Sponsorship	Japan Soc. of Appl. Phys. IEEE Electron Devices Soc
Starting Page	118
Ending Page	119
File Size	860564
Page Count	2
File Format	PDF
ISBN	4900784001
DOI	10.1109/.2005.1469235
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-06-14
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	JSAP
Subject Keyword	SONOS devices Nonvolatile memory Space technology Transistors Scalability Silicon compounds Computer science Research and development Semiconductor device reliability Electron traps
Content Type	Text
Resource Type	Article

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