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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Sung Kee Han Hyung-Suk Jung Hajin Lim Min Joo Kim Cheol-kyu Lee Mong sub Lee Young-sub You Hion Suck Baik Young Su Chung Eunha Lee Jong-Ho Lee Nae In Lee Ho-Kyu Kang |
| Copyright Year | 2006 |
| Description | Author affiliation: Syst. LSI Div., Samsung Electron. Co., Yongin (Sung Kee Han; Hyung-Suk Jung; Hajin Lim; Min Joo Kim) |
| Abstract | The authors have successfully developed a mass production friendly single metal gate process utilizing an ultra-thin metal inserted poly-Si stack (UT-MIPS) structure. First, the inserted metal gate thickness effects on device performances are carefully examined, and then the other parameters are optimized to give the best performance. As a results, low and symmetrical short channel Vth (0.44/-0.48 V for n/pMOS) and excellent drive currents (620/230 muA/mum for n/pMOS at Ioff =20pA/mum and Vdd=1.2 V) are obtained without using any mobility enhancement strain technology. The estimated operation voltage for 10 years lifetime of optimized UT-MIPS devices (1.25 V for nMOS PBTI and 1.5 V pMOS NBTI) are well beyond the 1.2 V, showing the good reliability characteristics of UT-MIPS devices as well |
| Starting Page | 1 |
| Ending Page | 4 |
| File Size | 513943 |
| Page Count | 4 |
| File Format | |
| ISBN | 142440438X |
| DOI | 10.1109/IEDM.2006.346860 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2006-12-11 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Manufacturing processes Mass production Optimized production technology Dielectrics Large scale integration Research and development Capacitive sensors Life estimation Lifetime estimation Voltage |
| Content Type | Text |
| Resource Type | Article |
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