NDLI: Thermal and spatial profiling of TSV-induced stress in 3DICs

Content Provider	IEEE Xplore Digital Library
Author	McDonough, C. Backes, B. Wei Wang Geer, R.E.
Copyright Year	2011
Description	Author affiliation: College of Nanoscale Science and Engineering, University at Albany, SUNY, NY, USA (McDonough, C.; Backes, B.; Wei Wang; Geer, R.E.)
Abstract	The thermal and spatial variation of Cu through silicon via (TSV)-induced stress in 300mm Si wafers has been investigated for both isolated TSVs and TSV arrays using top-down and cross-sectional spectral microRaman imaging. The TSV-induced stress in Si results from plastic yield of the Cu, is compressive in the immediate vicinity of the TSV, and transitions to a tensile state at larger separations - in quantitative agreement with finite element modeling (FEM). TSV arrays (linear and square) lead to substantial tensile stress enhancement within the array. Moreover, thermal annealing showed that the intra-array Si stress field became more compressive with increased post-CMP thermal annealing while the Si stress-field external to the arrays exhibited little change. This may open potential avenues for reduction of TSV-induced Si stress in 3DICs.
File Size	848627
File Format	PDF
ISBN	9781424491131
ISSN	19381891
e-ISBN	9781424491124
e-ISBN	9781424491117
DOI	10.1109/IRPS.2011.5784530
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-04-10
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Silicon Through-silicon vias Copper Temperature measurement Annealing Tensile stress stress 3D integrated circuit through-silicon via
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in