NDLI: 3D integration technology and reliability

Content Provider	IEEE Xplore Digital Library
Author	Koyanagi, M.
Copyright Year	2011
Description	Author affiliation: New Industry Creation Hatchery Center (NICHe), Tohoku University, Sendai, 980-8579 Japan (Koyanagi, M.)
Abstract	Three-dimensional (3D) integration technologies including a new 3D heterogeneous integration of super-chip are described. In addition, reliability issues in these 3D LSIs such as mechanical stresses induced by through-silicon vias (TSVs) and metal microbumps and Cu contamination in thinned wafers are discussed. Cu TSVs with the diameter of 20µm induced the maximum compressive stress of ∼1 GPa at the silicon substrate adjacent to them after annealed at 300°C for 30 min. Mechanical strain/stress and crystal defects were produced in extremely thin wafers (thickness ∼10µm) of 3D LSIs not only during wafer thinning, but also after wafer bonding using fine-pitch, high-density metal microbumps and curing. The influence of Cu contamination at the back surface of the thinned wafer has been evaluated by C-t analysis. C-t curves measured in MOS capacitors without IG layer and EG layer were seriously degraded after annealing even at 200°C whereas the C-t curves exhibited only a little change even after annealing up to 350 min at 300°C. It was revealed that the generation lifetime of minority carrier is significantly reduced by the Cu contamination.
File Size	1951923
File Format	PDF
ISBN	9781424491131
ISSN	19381891
e-ISBN	9781424491124
e-ISBN	9781424491117
DOI	10.1109/IRPS.2011.5784496
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-04-10
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Silicon Stress Copper Substrates Three dimensional displays Bonding Cu contamination 3D LSI TSV Microbump Mechanical stress
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

3D integration technology and reliability challenges

3D LSI and reliability

3D LSI technology and reliability issues

3D TSV mid-end processes and assembly/packaging technology

Thermomechanical reliability challenges induced by high density Cu TSVs and metal micro-joining for 3-D ICs

3D integration of standard integrated circuits

Wafer thinning for high-density three dimensional integration _ 12-inch wafer-level 3D-LSI program at GINTI

3D integration technology using hybrid wafer bonding and via-last TSV process

High density and reliable packaging technology with Non Conductive Film for 3D/TSV

3D integration technology and reliability

Similar Documents

3D integration technology and reliability challenges

3D LSI and reliability

3D LSI technology and reliability issues

3D TSV mid-end processes and assembly/packaging technology

Thermomechanical reliability challenges induced by high density Cu TSVs and metal micro-joining for 3-D ICs

3D integration of standard integrated circuits

Wafer thinning for high-density three dimensional integration _ 12-inch wafer-level 3D-LSI program at GINTI

3D integration technology using hybrid wafer bonding and via-last TSV process

High density and reliable packaging technology with Non Conductive Film for 3D/TSV

3D integration technology and reliability