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Content Provider | IEEE Xplore Digital Library |
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Author | Shrivastava, M. Bychikhin, S. Pogany, D. Schneider, J. Shojaei Baghini, M. Gossner, H. Gornik, E. Ramgopal Rao, V. |
Copyright Year | 2010 |
Description | Author affiliation: Center for Excellence in Nanoelectronics, Department of Electrical Engineering, Indian Institute of Technology-Bombay, Mumbai-400076, India (Shrivastava, M.; Shojaei Baghini, M.; Ramgopal Rao, V.) || Institute for Solid State Electronics, Vienna University of Technology, Austria (Bychikhin, S.; Pogany, D.; Gornik, E.) || Infineon Technologies AG, P.O. Box 80 09 49, D-81609 Munich, Germany (Schneider, J.; Gossner, H.) |
Abstract | We present differences in the ESD failure mechanisms, intrinsic behavior and various phases of filamentation of STI type DeNMOS and DePMOS devices using detailed 3D TCAD simulations, TLP and TIM experiments. The impact of localized base-push-out, power dissipation because of space charge build-up, regenerative bipolar triggering and various events during the current filamentation are compared. Measurements show that the absence of base push out in DePMOS device leads to ∼2.5X higher IT2 as compared to DeNMOS. |
Starting Page | 480 |
Ending Page | 484 |
File Size | 1226800 |
Page Count | 5 |
File Format | |
ISBN | 9781424454303 |
ISSN | 19381891 |
e-ISBN | 9781424454297 |
DOI | 10.1109/IRPS.2010.5488785 |
Language | English |
Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher Date | 2010-05-02 |
Publisher Place | USA |
Access Restriction | Subscribed |
Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subject Keyword | MOS devices Electrostatic discharge Doping Failure analysis Electrostatic interference Space charge Fingers CMOS process CMOS technology Silicon Filamentation DEMOS ESD Failure space charge buildup |
Content Type | Text |
Resource Type | Article |
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