NDLI: A built-in aging detection and compensation technique for improving reliability of nanoscale CMOS designs

Content Provider	IEEE Xplore Digital Library
Author	Dadgour, H.F. Banerjee, K.
Copyright Year	2010
Description	Author affiliation: Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA 93106, USA (Dadgour, H.F.; Banerjee, K.)
Abstract	The time-dependent degradation (aging) of device characteristics caused by Bias Temperature Instability (BTI) and Hot-Carrier Injection (HCI) are one of the major threats to the reliability of nanoscale digital CMOS designs. To address this challenge, a novel built-in aging “detection” and “compensation” technique is proposed. Performance degradation is detected using a novel area- and power-efficient sensor. Then, to improve the reliability, an adaptive Time-Borrowing (TB)-based compensation technique is employed, which decreases the timing failure probabilities in spite of aged transistors. It is shown via simulations that by employing these techniques, the reliability of circuits can be improved by approximately 10X.
Starting Page	822
Ending Page	825
File Size	449082
Page Count	4
File Format	PDF
ISBN	9781424454303
ISSN	19381891
e-ISBN	9781424454297
DOI	10.1109/IRPS.2010.5488727
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-05-02
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Aging Circuits Degradation Voltage Timing Flip-flops Nanoscale devices Human computer interaction Sensor phenomena and characterization Detectors Timing Analysis Bias-Temperature Instability Diagnostics Fault-Tolerance Hot-carrier Effect NBTI PBTI Process Variation Reliability Robustness
Content Type	Text
Resource Type	Article

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