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Content Provider | IEEE Xplore Digital Library |
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Author | Eun Suk Cho Hyun Jung Kim Byoung Taek Kim Jai Hyuk Song Du Heon Song Jeong-Hyuk Choi Kang-Deog Suh Chilhee Chung |
Copyright Year | 2010 |
Description | Author affiliation: School of Information and Communication Engineering, Sungkyunkwan University, Suwon, 440-746, South Korea (Kang-Deog Suh) || NAND Flash Process Architecture Team, Semiconductor Business Division, Samsung Electronics Co., San #24, Nongseo-Dong, Giheung-Gu, Yongin-City, Gyunggi-Do 446-711, Korea (Eun Suk Cho; Hyun Jung Kim; Byoung Taek Kim; Jai Hyuk Song; Du Heon Song; Jeong-Hyuk Choi; Chilhee Chung) |
Abstract | One of the critical scaling barriers in sub 30 nm NAND Flash technology node is an abrupt threshold voltage drop of cell transistors by short channel effect. It increases program voltage which leads, in turn, to fatal reliability issues. A simple way to relieve the short channel effect is increasing the channel boron concentration. However it degrades endurance characteristics by deteriorating boosting efficiency on inhibit operation. In this paper, we present an optimal cell design for the improved reliability characteristics in the level of mass production for the future NAND Flash with floating gate cells. |
Starting Page | 611 |
Ending Page | 614 |
File Size | 342937 |
Page Count | 4 |
File Format | |
ISBN | 9781424454303 |
ISSN | 19381891 |
e-ISBN | 9781424454297 |
DOI | 10.1109/IRPS.2010.5488763 |
Language | English |
Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher Date | 2010-05-02 |
Publisher Place | USA |
Access Restriction | Subscribed |
Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subject Keyword | Boron Threshold voltage Nonvolatile memory Degradation Interference Doping Business communication Boosting Mass production Temperature NAND Flash Reliability SCE Coupling Rario Floating Gate |
Content Type | Text |
Resource Type | Article |
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