NDLI: Low power adaptive pipeline based on instruction isolation

Content Provider	IEEE Xplore Digital Library
Author	Seung Eun Lee Wilkerson, C. Ming Zhang Yavatkar, R. Shih-Lien Lu Bagherzadeh, N.
Copyright Year	2009
Description	Author affiliation: University of California, Irvine, USA (Seung Eun Lee; Bagherzadeh, N.) \|\| Intel Corporation, Hillsboro, OR USA (Wilkerson, C.; Ming Zhang; Yavatkar, R.; Shih-Lien Lu)
Abstract	One of the most effective techniques to reduce a processor's power consumption is to reduce supply voltage. However, reducing voltage in the context of parameter variations can cause circuits to fail. As a result, voltage scaling is limited by a minimum voltage, often called Vccmin, beyond which circuits may not operate reliably. In this paper, we propose an architectural technique that enables microprocessor to operate at low voltage, while maintaining high frequency operations based on instruction isolation. The instruction isolation scheme isolates the set of possible instructions that do not complete within the clock period at the scaled Vcc and avoids possible timing errors in the instructions by dynamically adapting the clock period. Compared to current design, our scheme enables extra 13% average power saving.
Starting Page	788
Ending Page	793
File Size	499799
Page Count	6
File Format	PDF
ISBN	9781424429523
DOI	10.1109/ISQED.2009.4810393
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-03-16
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Pipelines Circuits Microprocessors Frequency Clocks Timing Temperature Energy consumption Low voltage Maintenance ALU Low Power Design Voltage Scaling Reliability
Content Type	Text
Resource Type	Article

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