NDLI: Adaptive voltage controlled nanoelectronic addressing for yield, accuracy and resolution

Content Provider	IEEE Xplore Digital Library
Author	Bao Liu
Copyright Year	2009
Description	Author affiliation: Electrical and Computer Engineering Department, The University of Texas at San Antonio, 78249-0669, USA (Bao Liu)
Abstract	An outstanding challenge for realizing nanoelectronic systems is nano-interface design, i.e., how to precisely access a nanoscale wire in an array for communication between a nanoscale system and the outside world. Existing nanoelectronic addressing methods are based on implementation of binary decoders, which requires unrealistic precise layout design in nanotechnology. In this paper, I propose voltage controlled nanoelectronic addressing, which differentiates each nanoscale wire by their electrical parameters, e.g., voltages, instead of required unique physical structures. As a result, voltage controlled nanoelectronic addressing achieves significant yield improvement, which enables aggressive scaling of nano-interface with the rest of a nanoscale system. A novel nanoelectronic addressing circuit includes two address lines which form resistive voltage dividers, and provide gate voltages for two rows of transistors which gate the nanoscale data lines. For two proposed nanoelectronic addressing metrics: resolution and accuracy, the proposed circuit achieves single data line resolution by applying high voltage drops to the address lines if not high subthreshold slope transistors, while an adaptive addressing method achieves addressing accuracy only depending on the uniformity of the address lines, and external time domain variations. SPICE simulation based on compact CNFET models demonstrates the effectiveness of voltage controlled nanoelectronic addressing.
Starting Page	430
Ending Page	435
File Size	494645
Page Count	6
File Format	PDF
ISBN	9781424429523
DOI	10.1109/ISQED.2009.4810333
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-03-16
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Programmable control Adaptive control Voltage control Communication system control Wire Circuits Decoding Nanotechnology Control systems SPICE
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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